Power Control Circuit for Semiconductor IC Data Retention
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Solution Overview
Problem
As semiconductor ICs are scaled down, power leakage increases, leading to challenges in reducing current leakage while maintaining data integrity, especially in portable devices, where power gating schemes cause data loss and retention flip-flops occupy more IC space.
Innovation Solution
A power control circuit that switches between main power voltage and a minimally sufficient retention voltage to maintain data integrity without the need for data backup and recovery, using a controller, power gating circuit, and charge pumps to manage voltage levels in a semiconductor IC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating schemes are used to reduce current leakage, then power consumption is reduced, but data integrity is lost
Solution Approach 1:
The power supply system is segmented into two distinct voltage levels: main power voltage for full operation and retention voltage for data preservation. This segmentation allows the logic block to operate at full power during normal operation and switch to retention voltage during power-down, simultaneously achieving low power consumption and data integrity preservation.
Solution Approach 2:
The patent changes the voltage parameter from full main power voltage to a reduced retention voltage level during power-down mode. This parameter change enables the logic block to maintain data integrity without requiring full power operation, thus reducing power consumption while preserving data.
2Loss of information
If retention flip-flops are used to maintain data without power, then data integrity is preserved, but IC area increases
Solution Approach 1:
The logic block's existing flip-flops are made multi-functional by enabling them to operate in retention mode with reduced voltage. Instead of requiring separate retention flip-flops, the same flip-flop structure serves both normal operation and data retention functions, thereby preserving data integrity without increasing IC area.
Solution Approach 2:
By changing the voltage parameter to a reduced retention voltage level, the existing flip-flop structures can maintain data integrity without requiring additional retention-specific hardware. This parameter change enables the same physical structure to serve multiple purposes, avoiding area expansion.
3Loss of information
If data backup and recovery operations are performed, then data integrity is maintained, but operation speed decreases
Solution Approach 1:
The system performs preliminary action by maintaining data integrity through retention voltage before power is completely interrupted. This eliminates the need for subsequent data backup and recovery operations, thereby avoiding the speed penalty associated with these operations while ensuring data integrity is preserved.
Solution Approach 2:
The useful action of data storage continues uninterrupted by maintaining retention voltage during power-down. Instead of stopping data storage and performing backup operations, the system maintains continuous data integrity through the retention voltage, thereby avoiding the time loss associated with backup and recovery operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and IC size by maintaining data integrity without the need for data backup and recovery operations, while minimizing power loss and IC area usage.
Implementation Method 1
a charge pump responsive to a charge pump control signal and the main power voltage to pump up a voltage apparent at the output terminal
Data Source
AI summary
A power control circuit and related method providing power to an output terminal supplying a logic block within a semiconductor integrated circuit are disclosed. The power control circuit includes a power gating circuit providing a main power voltage to the output terminal during a normal operating mode and providing a retention voltage to the output terminal during a data retention mode characterized by the absence of the main power voltage from the logic block, wherein the retention voltage is minimally sufficient to retain data stored in the logic block during the data retention mode.