Power Control Circuit for Semiconductor Voltage Transient Management
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Solution Overview
Problem
Existing semiconductor devices face challenges in minimizing voltage and current transients during power mode changes, which can lead to power on reset due to increased load on voltage supplies as transistors and components shrink.
Innovation Solution
A power control circuit using a series of P-channel and N-channel transistors and comparators that gradually increase the supply voltage by turning on switches in succession based on progressively higher voltage thresholds, maintaining a constant current level and reducing stress on external circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of devices is increased to handle greater load, then productivity is improved, but voltage supply stability deteriorates due to increased transient effects
Solution Approach 1:
The power supply system is segmented into multiple stages with individual control for each voltage node. Each stage includes separate PMOS transistors (first, second, third PMOS) and NMOS transistors that can be independently controlled, allowing gradual voltage application to different device groups to minimize transient effects while supporting increased device capacity
Solution Approach 2:
The system performs preliminary actions by pre-charging capacitance nodes and applying voltage in a controlled sequence before full power operation. The first PMOS transistor is activated early to pre-charge nodes, and voltage is applied progressively through multiple stages rather than all at once, preventing power-on reset conditions
2Productivity
If transistor size is reduced to increase device density, then productivity is improved, but voltage supply stability deteriorates due to increased load on voltage supply
Solution Approach 1:
The voltage supply system is divided into multiple segmented stages, each with its own control transistors and capacitance nodes. This segmentation allows the total load from high-density devices to be distributed across multiple controlled stages, preventing any single stage from experiencing excessive transient current that would destabilize the voltage supply
Solution Approach 2:
The system dynamically adjusts the activation sequence and timing of control transistors based on voltage thresholds. As devices are powered on in stages, the control logic dynamically manages which PMOS and NMOS transistors are active, adapting to changing load conditions to maintain voltage stability despite reduced transistor sizes
3Power
If voltage is increased rapidly to meet power demands, then power delivery is improved, but harmful effects increase due to voltage transients causing power on reset
Solution Approach 1:
The system performs preliminary voltage application through the first PMOS transistor to charge capacitance nodes before activating the main power delivery path. This preliminary action ensures that voltage is already present at critical nodes when full power is applied, eliminating voltage transients and preventing power-on reset conditions while still meeting power delivery requirements
Solution Approach 2:
Capacitance nodes and control transistors act as intermediaries between the power supply and the device circuitry. These intermediaries buffer and smooth the voltage transition, preventing direct coupling of rapid voltage changes to the devices and thereby eliminating harmful transient effects while maintaining adequate power delivery
4Reliability
If inrush current is reduced to protect circuitry, then reliability is improved, but power delivery capability deteriorates
Solution Approach 1:
The power delivery path is segmented into multiple parallel branches with individual control. The first PMOS transistor controls a pre-charge path with limited current, while the second and third PMOS transistors control main power paths that can deliver full current. This segmentation allows circuitry protection during initial power-up while maintaining full power delivery capability when needed
Solution Approach 2:
The system performs preliminary power delivery through the first PMOS transistor to establish minimum voltage levels and charge essential capacitance nodes. This preliminary action protects circuitry from inrush current while still providing sufficient power for initial operation, after which additional power paths are activated to meet full power demands
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively regulates supply voltage and current, minimizing transients and preventing power on reset during mode changes, ensuring stable operation and reducing stress on semiconductor devices.
Implementation Method 1
a first transistor coupled between a power supply node and a gated voltage supply node, each having a control electrode
Implementation Method 2
A first voltage comparator has a first input and a first output coupled to the control gate of a second transistor. In response to assertion of the power control signal, the first input is coupled to the gated voltage supply node
Data Source
Figure 1~2
Figure 3
AI summary
A power control circuit includes a plurality of transistors coupled between a power supply node (VDD) and a gated power supply node (VDDi), wherein the gate electrode of a first transistor of the plurality of transistors (102, 104, 106) is coupled to receive a power control signal, wherein, in response to assertion of the power control signal, the first transistor is placed into a conductive state; a first voltage comparator (112), wherein, in response to assertion of the power control signal, places a second transistor of the plurality of transistors in a conductive state when a voltage on the gated voltage supply node reaches a first reference voltage; and a second voltage comparator (114), wherein, in response to assertion of the power control signal, places a third transistor of the plurality of transistors in a conductive state when the voltage on the gated voltage supply node reaches a second reference voltage different from the first reference voltage.