Power-Control Device with Variant Delay Chain for Dynamic Voltage Adjustment
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Solution Overview
Problem
Existing power control systems in electronic devices, such as mobile devices, face inefficiencies in reducing power consumption due to fixed dynamic voltage-frequency scaling (DVFS) tables that do not account for varying frequency-voltage characteristics among chips, leading to suboptimal operation and increased power usage.
Innovation Solution
A power-control device with a variant delay chain, sampling circuit, comparison circuit, power manager, clock generator, and temperature sensor that dynamically adjusts the supply voltage based on the operation frequency and ambient temperature, ensuring each chip operates at an optimal voltage level that matches its frequency-voltage characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a fixed DVFS table is applied for all chips in the same batch, then the control system is simple and easy to manufacture, but power consumption cannot be reduced for chips that can achieve the same expected operation frequency on lower voltages
Solution Approach 1:
The patent implements dynamic voltage-frequency scaling by making the DVFS table adjustable rather than fixed. The controller dynamically selects and applies different DVFS tables based on measured frequency-voltage characteristics of each chip, allowing the system to adapt to individual chip variations and achieve lower power consumption without excessive complexity
Solution Approach 2:
The system employs feedback mechanisms where the controller measures the actual operation frequency and voltage characteristics of each chip, then uses this feedback information to select the appropriate DVFS table. This closed-loop feedback enables the system to optimize power consumption by matching the DVFS table to the actual chip characteristics
2Use of energy by moving object
If the supply voltage is lowered to reduce power consumption, then power efficiency improves, but the operation frequency and performance may be compromised
Solution Approach 1:
The patent changes the parameters of the DVFS table itself, allowing different voltage-frequency mapping relationships to be applied. By selecting DVFS tables with different parameter sets that match the actual chip characteristics, the system can achieve lower power consumption while maintaining the required operation frequency and performance level
3Ease of manufacture
If a single DVFS table is used across all chips, then manufacturing and deployment are simplified, but chips with better frequency-voltage characteristics cannot operate at optimal voltage levels
Solution Approach 1:
The patent segments the single DVFS table into multiple distinct DVFS tables, each optimized for different frequency-voltage characteristic profiles. The controller measures the chip's characteristics and selects the appropriate segmented table, enabling customized power optimization for each chip while maintaining a standardized multi-table structure that simplifies manufacturing and deployment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for reduced power consumption while maintaining proper operation by dynamically adjusting the supply voltage, even when a single DVFS table is applied across all chips, ensuring better performance and efficiency.
Implementation Method 1
The temperature sensor senses an ambient temperature of the temperature sensor and generates a temperature signal according to the sensed ambient temperature
Implementation Method 2
When the power manager determines that the ambient temperature reaches an upper threshold according to the temperature signal, the power manager lowers a level of the supply voltage
Data Source
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AI summary
A power-control device for generating and controlling a supply voltage (Vsupply) is provided. The power-control device includes a variant delay chain (1000) with a delay length, a sampling circuit (1001), a comparison circuit (1002), and a power manager (101). The variant delay chain (1000) receives an initial signal (S1003) and performs a delay operation on the initial signal (S1003) according to the delay length to generate a delay signal (S1000). The sampling circuit (1001) receives the delay signal (S1000) and performs a sampling operation on the delay signal (S 1000) to generate a sampled signal (S1001). The comparison circuit (1002) receives the sampled signal (S1001) and compares the sampled signal (S1001) with a reference signal (S1004) to generate a comparison result signal (S1002). The power manager (101) receives the comparison result signal (S1002) and adjusts the supply voltage (Vsupply) according to the comparison result signal (S1002).