Power Control Unit Pending Write Completion Self-Refresh
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Solution Overview
Problem
Computer systems face challenges in ensuring that pending write requests are completed and data is preserved during power loss, particularly in volatile memory, without relying on large backup power sources or complex software implementations, and without violating write ordering rules.
Innovation Solution
A hardware-based flow is implemented using a power control unit to coordinate the completion of pending write requests and transition the system memory into self-refresh mode, blocking incoming writes and utilizing a battery backup unit for power, thereby reducing power usage and eliminating the need for software-based SMI handlers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large backup power source is used to preserve data during power loss, then data preservation reliability is improved, but power consumption and device complexity increase
Solution Approach 1:
The system performs preliminary actions by completing all pending write requests to volatile memory before transitioning to self-refresh mode. The memory controller ensures that data is written to volatile memory in advance, so that when power is lost, the data is already preserved in the volatile memory, eliminating the need for large backup power sources.
Solution Approach 2:
The volatile memory is placed in self-refresh mode, where it autonomously maintains its data without requiring external power or control signals. The memory controller transitions the memory to this self-sustaining state, allowing the memory to service itself and preserve data using minimal power from the backup source.
2Reliability
If software-based SMI handlers are used to manage power loss, then data preservation is improved, but device complexity and processing time increase
Solution Approach 1:
The patent replaces the software-based SMI handler mechanism with a hardware-based flow. The memory controller directly manages the transition to self-refresh mode and blocks incoming write requests through hardware logic, eliminating the need for software intervention and reducing processing time and complexity.
Solution Approach 2:
The complex software-based SMI handler is extracted and removed from the system. Instead, a simplified hardware-based flow is implemented that directly handles power loss scenarios, reducing device complexity while maintaining data preservation reliability.
3Reliability
If the system waits for pending write requests to complete before transitioning to self-refresh mode, then data integrity is improved, but transition time increases
Solution Approach 1:
The memory controller performs preliminary actions by proactively completing pending write requests and transitioning memory to self-refresh mode before power loss occurs. This preliminary completion of data writes ensures integrity without requiring extended waiting periods during the actual power loss event.
Solution Approach 2:
The hardware-based flow enables the system to rush through the transition process by directly blocking incoming writes and completing pending requests without software intervention delays. The system skips the time-consuming software handler execution and directly transitions to the self-refresh state, reducing overall transition time while maintaining data integrity.
Data Source
AI summary
In one embodiment, an apparatus comprises a processor core and a power control unit. The power control unit is to identify the occurrence of a power loss from a primary power source, instruct the I/O controller to block further write requests from the one or more I/O devices and to send at least one pending write request stored by the I/O controller to the memory controller, and instruct the memory controller to complete at least one pending write request stored by the memory controller and to cause the memory to be placed into a self-refresh mode.