Power Controller for Semiconductor Memory Leakage Reduction
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Solution Overview
Problem
Portable electronic devices require memory systems that balance low leakage currents with fast access and cycle times, a challenge not fully met by current technologies despite increasing functionality and smaller size.
Innovation Solution
A power controller and method for a semiconductor memory system that cycles memory between active and low leakage data retention states, with an expanded retain-till-access module extending the active state for a specified period before returning to low leakage, allowing for efficient power management across memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the memory is kept in active state to allow fast access, then access speed is improved, but leakage current increases
Solution Approach 1:
The memory system dynamically transitions between active state and low leakage data retention state based on access requirements. The power controller monitors access patterns and adjusts the memory state accordingly, making the system adaptable rather than static. This resolves the contradiction by allowing fast access when needed while reducing leakage during non-access periods.
Solution Approach 2:
The memory operates in periodic cycles, alternating between active state during access operations and low leakage data retention state during non-access periods. This periodic switching enables the system to achieve fast access when required while minimizing energy loss during idle times, effectively resolving the speed-leakage current tradeoff.
2Loss of energy
If the memory is cycled between active and low leakage states, then leakage current is reduced, but access time increases
Solution Approach 1:
The power controller predicts future access needs and maintains the memory in active state for a predetermined extended period after the last access. This preliminary action ensures that if another access is needed soon, the memory is already in the fast access state, avoiding the delay of state transitions and thus reducing effective access time while still managing leakage current.
Solution Approach 2:
The system uses feedback from access patterns and timing information to dynamically adjust when to transition between states. By monitoring access behavior and using this feedback to make intelligent decisions about state transitions, the system optimizes the balance between leakage reduction and access time, preventing unnecessary state changes that would increase access delay.
3Ease of operation
If the active state is extended for a specified period, then access readiness is improved, but power consumption increases
Solution Approach 1:
The system changes the time parameter of active state duration based on predicted access patterns. Instead of using a fixed extended active period, the power controller adjusts the duration dynamically according to feedback from actual access behavior. This parameter adaptation allows the system to maintain access readiness when beneficial while avoiding excessive power consumption when not needed.
Data Source
AI summary
Embodiments of the present disclosure provide a power controller, a method of operating a power controller and a semiconductor memory system. In one embodiment, the power controller is for use with a memory and includes an access module configured to provide an active state of the memory to allow memory access. The power controller also includes a retain-till-access module configured to cycle a portion of the memory between the active state and a low leakage data retention state of the memory. The power controller further includes an expanded retain-till-access module configured to extend the active state of the memory for a specified period of time before returning the memory to the low leakage data retention state.