Power Controller Overpower Protection Using Low Frequency Clock
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Solution Overview
Problem
Conventional switching power supplies lack effective protection mechanisms to prevent damage from over power, over current, and low voltage events, which can lead to dangerous fault conditions due to their continuous operation with AC mains.
Innovation Solution
A power controller incorporating a clock generator, low frequency clock generator, and protection circuit that periodically switches a power switch on and off, using a low frequency clock signal to detect over power events and isolate the power switch when an over power event lasts longer than a predetermined number of clock cycles, thereby preventing further power conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional switching power supplies operate continuously with AC mains, then power conversion efficiency is maintained, but protection against over power, over current, and low voltage events is insufficient leading to dangerous fault conditions
Solution Approach 1:
The low frequency clock generator serves multiple functions: it generates the low frequency clock signal for timing measurements, acts as a reference for the counter circuit, and enables the over-power protection function. This multi-functionality reduces the need for separate dedicated circuits for each protection function, thereby improving reliability without proportionally increasing device complexity
Solution Approach 2:
The counter circuit acts as an intermediary between the low frequency clock generator and the over-power protection logic. It counts the clock cycles to measure the duration of over-power events, providing a time-based measurement mechanism that enables precise protection timing without requiring complex analog timing circuits
2Reliability
If protection mechanisms are added to prevent damage from over power and over current events, then safety is improved, but circuit implementation cost increases
Solution Approach 1:
The protection circuit uses the power supply's own low frequency clock generator to provide the timing reference for over-power protection measurements. By utilizing existing internal resources rather than requiring external precision timing circuits, the solution improves safety while minimizing additional component requirements and manufacturing complexity
Solution Approach 2:
The invention changes the timing parameter from requiring high-precision external references to using the internally generated low frequency clock signal. This parameter change allows the protection circuit to be implemented using standard digital logic components that are cost-effective and easy to manufacture, while still providing accurate over-power duration measurement
3Reliability
If the power switch is isolated immediately upon detecting an over power event, then protection is timely, but the power supply cannot tolerate brief transient over power conditions
Solution Approach 1:
The counter circuit is pre-configured to count a predetermined number of clock cycles (corresponding to the over-power tolerance duration) before triggering the protection action. This preliminary setup of the counting mechanism enables the system to automatically tolerate transient over-power conditions while providing timely protection for sustained faults, resolving the contradiction between immediate protection and transient tolerance
Data Source
AI summary
A power controller includes a clock generator, a low-frequency clock generator, and a protection circuit. The clock generator provides a clock signal with a clock frequency for periodically switching on and off a power switch. The low-frequency clock generator provides a low-frequency clock signal with a frequency lower than the clock frequency. The protection circuit includes an over-power detection circuit and a logic circuit. The over-power detection circuit determines whether an over power event has occurred according to a feedback signal controlled by an output voltage of the power supply. When the over power event lasts longer than an over power tolerance duration, the logic circuit isolates the power switch from the clock signal to keep the power switch turned off. The over power tolerance duration is equal to a predetermined clock cycles of the low-frequency clock signal.