Power Conversion Circuit with Parallel Reactors for FET Loss Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing power conversion circuits, such as DC-DC converters and inverters, face significant steady losses in FETs due to high current densities, which are not effectively mitigated by existing soft-switching techniques.

Innovation Solution

A power conversion circuit design that includes a gate controller to manage the switching of n-channel FETs and diodes, ensuring specific timing and current flow conditions to minimize switching losses, where FETs are soft-switched by controlling their on-states to reduce current density and sharing current flow, thereby reducing steady losses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If FETs are switched alternately in conventional power conversion circuits, then voltage boosting is achieved, but current density in each FET becomes high causing large steady losses

Engineering Contradiction:
Improvevoltage boosting capabilityVSAvoidsteady loss in FETs
Core Design Contradiction:
PowerVSLoss of energy

Solution Approach 1:

The patent divides the current path into multiple parallel branches by introducing a second FET and associated reactors (first sub-reactor and second sub-reactor). This segmentation allows the total current to be distributed across multiple FETs, reducing the current density and steady losses in each individual FET while maintaining the overall voltage boosting function.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent combines multiple FETs and reactors into a unified circuit configuration where the first FET with first sub-reactor and second FET with second sub-reactor work cooperatively. This merging allows current sharing between parallel paths, reducing steady losses while achieving voltage boosting through the combined action of all components.

Inventive Principle:
Principle #5Merging (Combining)

2Device complexity

If current flows through single FET path, then circuit simplicity is maintained, but current density is high increasing steady losses

Engineering Contradiction:
Improvecircuit configurationVSAvoidsteady loss
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The patent introduces parallel current paths with additional FETs and reactors, segmenting the single current path into multiple paths. This increases device complexity but significantly reduces current density and steady losses through current sharing across the parallel branches.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution effectively suppresses steady losses in FETs during soft-switching operations, improving efficiency by ensuring balanced current flow and reduced switching and recovery losses across the circuit.

Implementation Method 1

when the first FET is turned off, a current flows through the first diode due to an induced voltage of the first sub-reactor. Moreover, when the second FET is turned off, a current flows through the second diode due to an induced voltage of the second sub-reactor

Methodology Applied
Scientific EffectElectromagnetic induction: Electromagnetic Induction

Data Source

PatentUS10305367B2Power conversion circuit
Publication Date: 2019.05.28 DENSO CORP
  • US10305367B2 patent drawing
  • US10305367B2 patent drawing
  • US10305367B2 patent drawing

AI summary

A power conversion circuit may include a first FET and a first diode connected in series between a second high potential wiring and a low potential wiring and a second FET and a second diode connected in series between the second high potential wiring and the low potential wiring. A main reactor may be connected to a first high potential wiring. A first sub-reactor may be connected between the main reactor and the first FET. A second sub-reactor may be connected between the main reactor and the second FET. First, second, third, and fourth periods repeatedly may appear in this order. In the third period, a first current flowing through the first sub-reactor decreases to zero after a timing at which the second FET is turned on, and the first FET is turned on after or on a timing at which the first current decreases to zero.