Dual-Controller Power Conversion Data Path for Soft Error Correction
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Solution Overview
Problem
The complexity and cost of the control board in each power conversion module of a modular uninterruptible power supply are increased by the requirement for three logic circuits and three communication paths to implement a majority decision determiner for soft error prevention.
Innovation Solution
A power conversion device with a simple configuration that includes two controllers connected in parallel, where data is repeatedly written and read from memory in accordance with a clock signal to correct soft errors, eliminating the need for a majority decision determiner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a majority decision determiner is implemented using three logic circuits and three communication paths, then soft error prevention capability is improved, but control board complexity and cost increase
Solution Approach 1:
The patent combines the soft error detection and correction functions into a single logic circuit that processes data from a single communication path. The controller integrates multiple functions (detection, verification, correction) into one unified processing unit, eliminating the need for separate majority decision determiners and multiple redundant communication paths.
Solution Approach 2:
The controller is designed to perform multiple functions: normal data processing, soft error detection, error verification, and error correction. This multi-functional approach allows a single controller to replace what would traditionally require separate dedicated circuits for each function, reducing overall system complexity.
2Reliability
If a majority decision determiner is implemented using three logic circuits and three communication paths, then soft error prevention capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines the soft error detection and correction functions into a single logic circuit that processes data from a single communication path. The controller integrates multiple functions (detection, verification, correction) into one unified processing unit, eliminating the need for separate majority decision determiners and multiple redundant communication paths.
Solution Approach 2:
Instead of using three separate communication paths and logic circuits, the patent uses a single path with a controller that creates virtual copies of the data processing function through software/firmware implementation. This digital copying approach is more cost-effective than physical hardware replication.
3Volume of moving object
If semiconductor devices are highly integrated and miniaturized to reduce size, then device miniaturization is achieved, but transient bit error occurrence increases
Solution Approach 1:
The controller implements self-service error correction by automatically detecting, verifying, and correcting soft errors in transmitted data without external intervention. The system monitors its own data transmission and processing, performing self-diagnosis and self-correction to maintain reliability despite miniaturization.
Solution Approach 2:
The patent implements a feedback mechanism where the controller receives transmitted data, compares it with expected values, and uses this feedback to detect and correct errors. The verification process provides continuous feedback on data integrity, allowing real-time correction of transient bit errors.
Data Source
AI summary
A first controller includes a first processor and a first memory. A second controller includes a second processor and a second memory. In transmitting data from the first controller to the second controller, the first controller repeatedly performs a write operation of writing transmitted data into the first memory in accordance with a clock signal, and reads the transmitted data from the first memory and outputs the transmitted data. The second controller writes the received data into the second memory in accordance with the clock signal, and reads the received data from the second memory in accordance with the clock signal. When a plurality of data values of the received data read from the second memory match each other in a plurality of consecutive clock cycles including a current clock cycle, the second controller transmits the data value of the current clock cycle to the second processor.