Power Converter Package Layout for EMI and Thermal Dissipation
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Solution Overview
Problem
Conventional power converters experience high electromagnetic interference (EMI) noise in high power density applications, leading to reduced switching frequency, increased thermal interface material thickness, compromised heat dissipation efficiency, and lower power density.
Innovation Solution
A power semiconductor package design featuring a lead frame with elevated sections and a metal-oxide-semiconductor field-effect transistor (MOSFET) chip, where the semiconductor chip is connected to a heat sink using thermal interface materials to minimize EMI noise, with the heat sink and thermal interface materials optimizing thermal dissipation and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional power converter design is used, then EMI noise is generated, but switching frequency must be reduced and thermal interface material thickness must be increased
Solution Approach 1:
The patent segments the thermal interface material into multiple layers with different functions: a first thermal interface material layer directly between the semiconductor device and heat sink, and a second thermal interface material layer between the elevated section and the first thermal interface material. This segmentation allows each layer to be optimized for specific purposes, reducing overall EMI while maintaining thermal performance.
Solution Approach 2:
The patent introduces an elevated section as an intermediary component between the semiconductor device and the heat sink. This elevated section acts as a mediator that reduces parasitic capacitance and EMI noise while still enabling effective thermal transfer, thus resolving the contradiction between EMI reduction and switching frequency maintenance.
2Object-affected harmful factors
If thermal interface material thickness is increased, then EMI noise is reduced, but heat dissipation efficiency decreases
Solution Approach 1:
The patent applies local quality by creating an elevated section with specific geometric characteristics (elevated height and width dimensions) that provide EMI shielding in the critical local area between the semiconductor device and heat sink, while maintaining thin thermal interface material layers for optimal heat dissipation. The elevated section's specific dimensions are optimized to provide EMI reduction without compromising thermal performance.
3Power
If power density is increased, then application performance is improved, but EMI noise and thermal management challenges increase
Solution Approach 1:
The patent adds a vertical dimension by creating an elevated section that rises above the conventional planar structure. This dimensional change provides EMI shielding capability without increasing the horizontal footprint, thus maintaining high power density while reducing EMI noise. The elevated section extends in the vertical direction to provide effective EMI protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes EMI noise, enhances thermal dissipation, and maintains high power density, suitable for applications above 1,200 kilowatts per cubic meters, such as USB-C chargers and electric vehicle on-board chargers.
Implementation Method 1
the semiconductor chip is connected to a heat sink using thermal interface materials to minimize EMI noise, with the heat sink and thermal interface materials optimizing thermal dissipation
Data Source
AI summary
A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.