Power Converter Gate Signal Fixing for Current Stability
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Solution Overview
Problem
In power converters, during overmodulation, the asynchronous PWM leads to a decrease in the number of pulses near zero-cross of the output voltage fundamental wave, causing imbalance and beat phenomena in the load current, resulting in control errors and sudden changes in inverter output current due to limitations in fundamental wave frequency and carrier frequency.
Innovation Solution
A power converter design that includes an inverter circuit and a switching-signal generating unit, which calculates gate signals based on alternating-current voltage output amplitude and phase commands, fixing gate signals in specific periods centered on phase angles to maintain a stable ratio and phase angle for turning on/off, thereby controlling the inverter output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If asynchronous PWM is used in overmodulation state, then the pulse waveform can be generated, but the number of pulses decreases near zero-cross causing imbalance and beat phenomena in load current
Solution Approach 1:
The patent applies dynamics by making the carrier wave synchronous with the modulated wave frequency. The carrier wave frequency dynamically adjusts to match the modulated wave frequency, ensuring that the number of pulses remains constant even as the output voltage amplitude changes in overmodulation state. This dynamic synchronization prevents the pulse number reduction that causes current imbalance and beat phenomena.
Solution Approach 2:
The patent changes the parameter relationship between carrier wave frequency and modulated wave frequency. Instead of using a fixed asynchronous carrier frequency, the carrier frequency is changed to be proportional to the modulated wave frequency (Fc = k × Fm), where k is a constant. This parameter change ensures consistent pulse distribution across the output voltage cycle, eliminating the imbalance and beat phenomena in load current.
2Power
If the number of pulses is reduced to increase output voltage, then the modulation rate increases, but control error increases and sudden current changes occur
Solution Approach 1:
The patent uses dynamic synchronization where the carrier wave frequency adjusts proportionally with the modulated wave frequency. This dynamic relationship ensures that as the output voltage amplitude increases in overmodulation state, the carrier wave maintains appropriate pulse density, preventing control errors and sudden current changes while achieving the desired power output.
Solution Approach 2:
The patent implements feedback control by continuously monitoring the relationship between modulated wave and carrier wave frequencies. The switching signal generating unit uses this feedback to adjust the carrier wave frequency to maintain synchronous relationship, ensuring stable control accuracy even when operating at high modulation rates for increased output voltage.
3Device complexity
If fundamental wave frequency and carrier frequency are limited by application constraints, then the system design is simplified, but the output current exhibits pulsation and sudden changes
Solution Approach 1:
The patent changes the fundamental relationship between carrier frequency and modulated wave frequency from a fixed asynchronous relationship to a synchronous proportional relationship (Fc = k × Fm). This parameter change allows the system to maintain current stability and eliminate pulsation while keeping the frequency control system relatively simple, as the synchronization is achieved through direct frequency proportionality rather than complex control mechanisms.
Data Source
AI summary
A power converter fixes, in one cycle of an alternating-current voltage output command, a gate pulse signal to always output a direct-current input positive side terminal voltage value of an inverter circuit in a period X1 centering on a phase angle θ1 for higher potential, fixes a gate pulse signal to always output a direct-current input negative side terminal voltage value of the inverter circuit in a period X2 centering on a phase angle θ2 for lower potential, and outputs a gate pulse signal in which a ratio of a period Y1, which is obtained by excluding the periods X1 and X2 from a period between the phase angle θ1 and the phase angle θ2, and the first period X1, and a ratio of a period Y2, which is obtained by excluding the periods X1 and X2 from a period between the phase angle θ2 and a phase angle θ1+360 [deg].