Power Converter Connection Assembly With Low-Inductance PCB Paths
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Solution Overview
Problem
Existing semiconductor devices with power converter modules suffer from high parasitic inductance and electromagnetic interference (EMI) due to the large loop area induced by the power converter's electrical paths.
Innovation Solution
The semiconductor device incorporates a multi-layer package substrate with specifically designed first and second electrical paths that extend linearly through multiple layers, reducing the loop area and parasitic inductance, thereby minimizing EMI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional flat no-lead package structure is used, then ease of manufacture is improved, but parasitic inductance increases due to large loop area
Solution Approach 1:
The patent transitions from a traditional two-dimensional planar trace layout to a three-dimensional multi-layer structure with vertical vias. The electrical paths extend through multiple layers (first layer, second layer, third layer) connected by vias, creating a compact 3D configuration that reduces the horizontal loop area while maintaining electrical connectivity. This dimensional change allows the current path to fold vertically rather than expanding horizontally, directly reducing parasitic inductance.
Solution Approach 2:
The patent embeds multiple electrical paths within a compact multi-layer package structure. The first and second electrical paths are nested within the same package substrate, with traces and vias interconnected across layers. This nesting approach allows complex electrical routing to be contained within a small footprint, reducing the overall loop area without compromising manufacturing feasibility.
2Ease of operation
If large loop area is used for electrical paths, then ease of layout is improved, but electromagnetic interference increases
Solution Approach 1:
The patent uses vertical stacking of electrical paths across multiple layers to reduce the horizontal footprint of the current loop. By routing traces on different layers and connecting them through vias, the design confines the electromagnetic field to a smaller planar area, thereby reducing EMI radiation while maintaining layout simplicity through standardized multi-layer PCB techniques.
3Object-generated harmful factors
If multi-layer structure with extended electrical paths is used, then parasitic inductance is reduced, but device complexity increases
Solution Approach 1:
The patent divides the electrical connection path into discrete segments across multiple layers, with each layer containing specific trace segments and vias providing vertical interconnections. This segmentation allows independent optimization of each layer's routing while maintaining overall low-inductance performance, and facilitates modular manufacturing processes.
Solution Approach 2:
The multi-layer package substrate serves multiple functions simultaneously: it provides mechanical support, establishes electrical connections, defines the current loop geometry, and integrates the power converter module. This multi-functionality reduces the need for additional separate components or structures, offsetting the increased structural complexity with functional integration.
Data Source
AI summary
A semiconductor device includes a die with a power converter module. The power converter module includes an output port and a return port. The semiconductor device also includes a connection assembly that includes pads configured to be coupled to circuit components of a printed circuit board (PCB). The connection assembly also includes a first layer patterned to include a first trace that is coupled to one of the output port and the return port and a second trace that is coupled to the other of the output port and return port. A second layer of the connection assembly is patterned to provide a first via between the first trace and a third layer and a second via between the first trace and the third layer. The third layer is patterned to provide a portion of a first conductive path and a portion of a second conductive path.