Two-Stage Power Converter Frequency Control

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Solution Overview

Problem

Conventional synchronous power converter systems face performance issues due to inappropriate switching frequencies, leading to suboptimal operation of power converters and degradation of overall computer system performance, especially when generating low output voltages at high switching frequencies.

Innovation Solution

A two-stage power conversion architecture with a processor outputting a synchronous clock signal at a first switching frequency, and a second-stage power converter using a multiplied frequency control circuit to generate an output voltage at a second switching frequency, which is a multiple of the first, allowing for adjusted voltage characteristics to meet performance requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single switching frequency is used for all power converters to simplify system control, then device complexity is reduced, but overall system performance degrades due to inability to optimize individual converter characteristics

Engineering Contradiction:
Improvesystem controlVSAvoidoverall system performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The controller is designed with multi-functionality to manage multiple switching frequencies. It can generate control signals for different power converters at different frequencies (600 kHz or 2.4 MHz) based on their specific requirements, while still maintaining a unified control architecture that manages the entire system.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11431251B2Power converter, synchronous power converter system and method of determining switching frequency
Publication Date: 2022.08.30 ANPEC ELECTRONICS CORPORATION
  • US11431251B2 patent drawing
  • US11431251B2 patent drawing
  • US11431251B2 patent drawing

AI summary

A power converter, a synchronous power converter system and a method of determining switching frequency are provided. A processor is configured to output a synchronous clock signal corresponding to a first switching frequency. A plurality of first-stage power converters are coupled to the processor, and configured to generate a plurality of first output voltages corresponding to the first switching frequency according to the synchronous clock signal and a system voltage. At least one second-stage power converter is coupled to the processor and one of the plurality of first-stage power converters, and configured to generate a second output voltage corresponding to a second switching frequency according to the synchronous clock signal, a multiplied frequency control signal and one of the plurality of first output voltages. The second switching frequency is a multiple of the first switching frequency.