Power Converter Phase Error Correction via Delay-Locked Loop
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Solution Overview
Problem
Modern computer systems face challenges in generating regulated power supply voltages due to noise interference between multiple power converter circuits, which can lead to instability and insufficient phase error correction, especially when using low-gain phase-locked loop circuits.
Innovation Solution
A voltage regulator circuit that employs a combination of high-gain and low-gain control loops to manage phase differences between power converter circuits, using a delay-locked loop to generate a reference clock signal and ramp signals that mimic the behavior of the switch node, thereby reducing phase errors and improving stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple power converter circuits operate simultaneously to provide power supply, then power delivery capability is improved, but noise interference and instability increase
Solution Approach 1:
The patent implements periodic action by sequentially enabling multiple power converter circuits at different time intervals rather than operating them simultaneously. Each converter is activated in sequence during different phases of the operating cycle, which eliminates noise interference while maintaining overall power delivery capability through the combined output of all converters over time.
2Device complexity
If low-gain phase-locked loop circuits are used for phase error correction, then circuit complexity is reduced, but phase error correction effectiveness deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the phase error correction function into separate stages corresponding to different power converter circuits. Each converter circuit has its own dedicated phase-locked loop circuit that operates independently to correct phase errors for its specific timing phase. This segmentation allows each low-gain PLL to focus on a narrow phase range, improving correction effectiveness without increasing overall system complexity.
Solution Approach 2:
The patent implements parameter changes by adjusting the gain characteristics of phase-locked loop circuits based on operating conditions. The system dynamically modifies PLL parameters such as loop bandwidth and gain factors to optimize phase error correction effectiveness across different operating scenarios, allowing low-gain circuits to achieve high correction performance when needed.
3Ease of operation
If phase differences between power converter circuits are not properly managed, then circuit operation is simplified, but stability deteriorates
Solution Approach 1:
The patent implements feedback mechanisms that automatically monitor and adjust phase differences between power converter circuits. Phase detectors continuously compare the timing of switching signals across converters and provide feedback to control circuits, which then adjust timing parameters to maintain optimal phase relationships. This feedback control ensures stability while requiring minimal manual intervention, preserving ease of operation.
Data Source
AI summary
A power converter circuit included in a computer system may charge and discharge a switch node coupled to a regulated power supply node via an inductor. The power converter circuit may generate a reference clock signal using a system clock signal and a voltage level of the switch node. The reference clock signal may be used to initiate a charge cycle, whose duration may be based on generated ramp signals.