Power Converter Serial Interface with Unified Multi-Protocol Decoding
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Solution Overview
Problem
Conventional power converters face challenges in efficiently managing serial communication protocols, leading to issues with space constraints in ASIC designs due to multiple protocols requiring different registers, and lack of flexibility in supporting changing specifications, which limits downstream feature enhancements.
Innovation Solution
A system with processing hardware, storage hardware, and serial communication hardware that selects and implements multiple serial communication protocols, using a repository of command decode functions to execute commands and manage telemetry data, allowing for flexible protocol support and efficient use of resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple serial communication protocols are implemented in an ASIC circuit, then protocol support capability is improved, but device area increases due to large number of registers required for each protocol
Solution Approach 1:
The patent implements a universal command decode function that can handle multiple serial communication protocols (I2C, SPI, 1-Wire) through a single unified interface. The system uses a protocol identification mechanism that detects the incoming protocol type and routes commands to appropriate handling routines, eliminating the need for separate dedicated hardware for each protocol and reducing overall device area while maintaining multi-protocol support capability
Solution Approach 2:
The system dynamically changes operational parameters based on the detected protocol type. When a command is received, the system identifies the protocol (I2C, SPI, or 1-Wire) and adjusts its internal state machine, register access patterns, and data formatting accordingly. This parameter-based adaptation allows a single set of hardware resources to serve multiple protocols efficiently
2Ease of manufacture
If conventional ASIC design techniques are used to implement serial communication protocols, then initial functionality is achieved, but flexibility for future protocol changes and feature enhancements is lost
Solution Approach 1:
The patent implements a dynamic protocol handling architecture where the command decode function can be reconfigured at runtime. The system includes a protocol registration mechanism that allows new protocol handlers to be added without hardware modification. The state machine is designed to be programmable, enabling future protocol additions through software updates rather than requiring ASIC re-spin, thus maintaining manufacturing simplicity while enabling future adaptability
Solution Approach 2:
The system segments the protocol handling into modular components: protocol identification module, command parsing module, and protocol-specific execution module. This segmentation allows individual protocol handlers to be developed, tested, and updated independently. The modular architecture enables future protocol additions by simply adding new modular components without affecting the core ASIC design, preserving both ease of manufacture and future flexibility
3Reliability
If separate registers are allocated for each serial communication protocol, then protocol-specific control is achieved, but space constraints in ASIC design worsen
Solution Approach 1:
The patent merges the register spaces of multiple protocols into a unified register map. Instead of having separate I2C registers, SPI registers, and 1-Wire registers, the system uses a single set of registers that are interpreted differently based on the active protocol. For example, a single control register may serve as the I2C control register when I2C is active, and as the SPI control register when SPI is active, eliminating redundant register allocations and reducing overall register space requirements
Solution Approach 2:
The patent introduces an intermediary protocol abstraction layer between the hardware registers and the protocol-specific processing logic. This intermediary layer provides a unified register interface that translates protocol-specific register accesses into internal standardized operations. The abstraction layer maintains protocol-specific control by translating diverse protocol register operations into a common internal representation, reducing the need for separate physical registers for each protocol
Data Source
AI summary
An apparatus includes processing hardware, storage hardware, and serial communication hardware. The processing hardware receives selection of a serial communication protocol. The serial communication protocol is selected amongst multiple serial communication protocols to control operation of a power converter. Via the processing hardware or other suitable entity, the storage hardware is populated with a set of command decode functions (a.k.a., command descriptors) assigned to the selected serial communication protocol. During operation, the serial communication hardware receives commands over a serial communication interface and executes the received commands via the set of command decode functions in the storage hardware. Each of the multiple commands communicated over the serial communication interface is encoded in accordance with the selected serial communication protocol. The serial communication hardware uses the set of command decode functions to execute the received commands.