Power Cut-Off Switch Placement for Voltage Drop and Routability

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Solution Overview

Problem

The installation of multiple power cut-off switches in the power cut-off region of semiconductor integrated circuit devices reduces the number of wiring channels, worsening routability and increasing voltage drop due to resistance in the power supply wiring.

Innovation Solution

Locating the power cut-off switch outside the power cut-off region and using a substrate-side feed line to transmit power-supply voltage back into the semiconductor chip, allowing for a larger cross-sectional area of wiring on the substrate to reduce resistance and voltage drop without reducing the degree of freedom in routing signal wiring.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If multiple power cut-off switches are installed in the power cut-off region, then voltage drop is suppressed, but the number of wiring channels is reduced and routability worsens

Engineering Contradiction:
Improvevoltage dropVSAvoidroutability
Core Design Contradiction:
Loss of energyVSAdaptability or versatility

Solution Approach 1:

The power supply system is segmented into two parts: power cut-off switches are placed in the substrate (package side) while power supply wiring is provided in the semiconductor chip. This segmentation allows voltage drop suppression through multiple switches without consuming wiring channels in the power cut-off region, resolving the contradiction between voltage stability and routability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention moves the power cut-off switches from the semiconductor chip plane to the substrate plane (another dimension), allowing power supply wiring to be provided in the chip without occupying signal wiring channels. This dimensional transition resolves the conflict between voltage drop suppression and routing flexibility.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If power cut-off switches are installed in the power cut-off region, then power supply control is improved, but wiring channel availability is reduced

Engineering Contradiction:
Improvepower supply controlVSAvoidwiring channel count
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The device is segmented into substrate and semiconductor chip components, with power cut-off switches located in the substrate and power supply wiring in the chip. This segmentation maintains reliable power control while preserving wiring channel availability in the power cut-off region for signal routing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The substrate acts as an intermediary layer that hosts the power cut-off switches, mediating between the external power supply and the semiconductor chip. This intermediary arrangement provides power control functionality without complicating the internal wiring of the power cut-off region.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8674756B2Power cut-off technique for semiconductor device
Publication Date: 2014.03.18 RENESAS ELECTRONICS CORP
  • US8674756B2 patent drawing
  • US8674756B2 patent drawing
  • US8674756B2 patent drawing

AI summary

Disclosed here is a semiconductor integrated circuit device configured to suppress a voltage drop over the route for transmitting voltages from a power cut-off switch to a power cut-off region without lowering the degree of freedom in routing signal wires in that region. The semiconductor integrated circuit device includes a semiconductor chip in which the power cut-off switch and power cut-off region are provided. A reduction in the number of wiring channels in the power-cut off region is avoided by locating the power cut-off switch outside the power cut-off region. Over the substrate, a substrate-side feed line is formed to transmit a power-supply voltage from the semiconductor chip to outside thereof via the power cut-off switch, before introducing the voltage again into the chip to feed the power cut-off region, thus suppressing the voltage drop between the power cut-off switch and the power cut-off region.