Memory Read Voltage Offset Calibration After Power Cycling

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Solution Overview

Problem

Slow charge loss (SCL) in memory systems leads to gradual changes in stored voltage levels, causing read command failures and increased latency due to error handling flows, especially in multi-level cell memory devices.

Innovation Solution

Determine a voltage offset for read operations after a power cycle by reading a sample page and calculating retention time, adjusting read voltages to compensate for SCL effects, thereby improving read performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If read operations are performed without voltage offset adjustment, then read operation speed is maintained, but read reliability deteriorates due to slow charge loss effects

Engineering Contradiction:
Improveread reliabilityVSAvoidread latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by calculating voltage offsets and retention times before performing read operations. The system determines voltage offsets during idle periods or power cycle events, then uses these pre-calculated offsets to adjust read voltages during subsequent read operations, eliminating the need for real-time calculations and avoiding read latency

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using read disturbance information and voltage offset calculations to continuously refine retention time estimates. The system monitors read operations, detects charge loss patterns, and adjusts voltage offsets based on feedback from actual read performance, creating a closed-loop system that improves reliability without sacrificing speed

Inventive Principle:
Principle #23Feedback

2Reliability

If voltage offset calculation is performed for every read operation, then read reliability is improved, but device complexity increases

Engineering Contradiction:
Improveread accuracyVSAvoidcontrol complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent reduces complexity by performing voltage offset calculations in advance during power cycle events or idle periods, rather than calculating offsets for every read operation. The calculated offsets are stored and reused for multiple subsequent reads, significantly reducing the computational burden during active read operations while maintaining high accuracy

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies partial action by performing complete voltage offset calculations only when necessary (e.g., after power cycles or when retention time exceeds thresholds), and using simplified or cached offset values for routine read operations. This selective approach maintains read accuracy while avoiding unnecessary computational complexity

Inventive Principle:
Principle #16Partial or excessive action

3Manufacturing precision

If retention time is calculated for each block, then manufacturing precision is improved, but loss of time increases due to calculation overhead

Engineering Contradiction:
Improvevoltage offset precisionVSAvoidcalculation time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent performs retention time calculations and voltage offset determinations in advance during manufacturing or initial device setup, storing these pre-calculated values for use during operation. This preliminary calculation approach ensures high precision voltage offsets are available without incurring calculation delays during production or normal operation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic retention time calculations at scheduled intervals or after specific events (such as power cycles or threshold time durations), rather than calculating for every read operation. This periodic approach maintains manufacturing precision while significantly reducing overall calculation time and computational overhead

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS12468464B2Read performance techniques for time retention
Publication Date: 2025.11.11 MICRON TECHNOLOGY INC
  • US12468464B2 patent drawing
  • US12468464B2 patent drawing
  • US12468464B2 patent drawing

AI summary

Methods, systems, and devices for read performance techniques for time retention are described. A memory system may store data in a block of memory cells and perform a power cycle operation. Based on performing the power cycle operation, the memory system may determine a first voltage offset associated with the block of memory cells by executing a first read command using an auto-read calibration operation. Based on the first voltage offset, and, in some examples, one or more additional voltage offsets, the memory system may calculate a retention time of data stored in the block of memory cells. The memory system may adjust a read voltage based on the retention time and perform one or more additional read commands.