Single-Interface Power and Data Signaling for Clock-Synced Links
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Solution Overview
Problem
Existing devices, such as earbuds and their cases, face challenges in efficiently coordinating communication and periodic updates, requiring improved data transfer methods to enhance accuracy and efficiency.
Innovation Solution
Implementing a data transmission scheme that combines communication and power transfer using eUSB2 signals, with asynchronous signal edges and fixed latency, and utilizing frame sync data for clock synchronization without digital processing, enabling efficient data replication and power coupling between devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate interfaces are used for power and data communication between host and devices, then communication accuracy and power transfer reliability are improved, but device complexity and coordination overhead increase
Solution Approach 1:
The patent combines power transfer and data communication into a single interface using eUSB2 signals. The host transmits both power and asynchronous data through the same physical connection, eliminating the need for separate interfaces and reducing coordination complexity while maintaining communication reliability through protocol-level separation of functions
2Reliability
If periodic updates are implemented between devices, then software enhancements and issue fixes are achieved, but communication coordination overhead and time loss increase
Solution Approach 1:
The patent implements periodic software updates through asynchronous communication where devices can initiate updates at optimized intervals without requiring synchronized coordination. The host and devices exchange update information using independent asynchronous signal edges, allowing periodic maintenance while minimizing coordination overhead and time loss
3Measurement precision
If digital processing is used for clock synchronization, then synchronization precision is improved, but processing complexity and power consumption increase
Solution Approach 1:
The patent replaces complex digital processing with a simpler electrical field-based synchronization mechanism. The host generates a clock signal that is electrically coupled to devices through the same interface used for power and data transfer. Devices derive synchronized clock frequencies directly from this electrical signal without requiring intensive digital processing, achieving accurate synchronization with reduced complexity and power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces jitter and ensures reliable, high-speed data transfer with synchronized clock frequencies, optimizing communication and power distribution between devices.
Implementation Method 1
a modem of the host receives asynchronous signal edges and transmits the asynchronous signal edges to the devices with a fixed latency. The modems of the devices replicate signal edges received from the host
Implementation Method 2
utilizing frame sync data for clock synchronization without digital processing, enabling efficient data replication and power coupling between devices
Implementation Method 3
coupling power with a communication data over the same signal between the host and the devices
Implementation Method 4
The electrical coupling network may be used to couple the single ended signal with power to provide a combination power and communication to a device
Data Source
AI summary
A host and one or more devices can communicate with each other using signals that couple communication data with power. The host can transmit the coupled data and the other device can decouple the communication data from the power. Further, the receiving device can replicate the transmitted communication signal without digital signal processing. The host and the devices can communicate with each other using a data frame in which one of the devices initially generates a first portion of the data frame and transmits the first portion, and the other device subsequently generates and transmits a second portion of the data frame. The data frame may include one or more frame sync data used to calibrate and align clock signals from clock circuits. Systems and methods for identifying data when a system is unaware of the protocol are also shown.