Power-On Detection Circuit With Delayed Comparator Enable

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Solution Overview

Problem

Conventional power-on-detection (POD) circuits in integrated circuits are prone to generating false power-on or reset signals due to the unsteady state of the reference voltage, leading to potential device malfunctions and failures.

Innovation Solution

The proposed POD circuit includes first and second comparators, a voltage divider, a detection circuit, and logic circuitry, where the detection circuit generates a control signal to control the turning on and off of the comparators, and the logic circuitry outputs a power identification signal based on the outputs of the comparators, with a capacitor providing a delay to stabilize the reference voltage before power detection, preventing false detection signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the POD circuit uses conventional comparator design without delay mechanism, then the power detection response is fast, but false power-on detection occurs due to unsteady reference voltage

Engineering Contradiction:
Improvepower detection response speedVSAvoidpower detection accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by introducing a delay mechanism that activates comparators only after the reference voltage has stabilized. The delay circuit generates a control signal that enables comparators at the appropriate time, preventing false detections caused by unsteady reference voltage while maintaining fast response once power is actually on.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses an intermediary delay circuit between the power supply and comparators. This delay circuit acts as a mediator that filters out transient unstable states of the reference voltage before they reach the comparators, allowing accurate power detection without false positives.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the POD circuit adds delay mechanism to stabilize reference voltage, then false detection is prevented, but response time increases

Engineering Contradiction:
Improvepower detection accuracyVSAvoidpower detection response time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The delay mechanism performs preliminary stabilization of the reference voltage before power detection begins. By enabling comparators only after the reference voltage has settled, the circuit ensures accurate detection while the delay period is minimized to only what is necessary for stabilization.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the temporal parameter of comparator activation by introducing a time delay. This parameter change allows the reference voltage to stabilize within a controlled time window, balancing the need for accuracy with minimal response time loss.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The improved POD circuit effectively prevents false power-on detection during power-up and reset operations by ensuring the reference voltage stabilizes before generating a power identification signal, thus enhancing the reliability of power supply management in integrated circuits.

Implementation Method 1

with a capacitor providing a delay to stabilize the reference voltage before power detection

Methodology Applied
Scientific EffectCapacitor delay: Capacitance

Data Source

PatentUS10267827B2Power on detection circuit
Publication Date: 2019.04.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10267827B2 patent drawing
  • US10267827B2 patent drawing
  • US10267827B2 patent drawing

AI summary

A power-on-detection (POD) circuit includes a detection circuit, first and second comparison circuits, and logic circuitry. The detection circuit includes a capacitor configured to charge from a first voltage level to a second voltage level. The first comparison circuit is configured to compare a third voltage level to a reference voltage level, and the second comparison circuit is configured to compare a fourth voltage level to the reference voltage level. The third and fourth levels are based on the second voltage level. The logic circuitry is coupled to an output of the first comparison circuit and to an output of the second comparison circuit and is configured to output a power identification signal based on the outputs of the first and second comparison circuits. The detection circuit is configured to turn on the first and second comparison circuits based on a voltage level of the capacitor.