Power Supply Detection Circuit With Hysteresis for Ramp-Up Glitch Suppression
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Solution Overview
Problem
Power supply circuits for integrated circuits face issues with unwanted voltage pulses, or glitches, during power ramp-up, which can lead to erroneous signals and excess current due to subthreshold voltages, and existing solutions require additional timing signals for synchronization.
Innovation Solution
A power supply detection circuit comprising a field effect transistor input stage, an inverter stage with complementary pairs of NMOS and PMOS transistors of varying gate lengths, a feedback stage with hysteresis, and optional filter capacitors and resistors to attenuate glitches and stabilize voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistors operate at subthreshold voltages during power ramp-up, then the power supply voltage rises and stabilizes, but unwanted voltage pulses or glitches are generated at the output
Solution Approach 1:
The patent introduces an intermediary detection circuit that monitors the power supply voltage and controls the enable signal to downstream circuits. This intermediary mechanism prevents direct transmission of glitches from the power ramp-up process to the output circuits, thereby eliminating the harmful voltage pulses while maintaining acceptable ramp-up speeds
Solution Approach 2:
The patent implements a feedback mechanism where the enable signal is controlled based on the detected power supply voltage level. The detection circuit provides feedback to prevent circuit activation during subthreshold conditions, thereby preventing glitch generation at the output while allowing controlled power ramp-up
2Reliability
If synchronization is used to reduce glitch effects, then erroneous signals are reduced, but additional timing signals are required between circuits
Solution Approach 1:
The patent employs a self-service approach where the power supply detection circuit automatically generates the enable signal based on its own voltage detection. This eliminates the need for external timing signals or synchronization mechanisms between circuits, reducing device complexity while maintaining signal accuracy through autonomous glitch prevention
Solution Approach 2:
The detection circuit acts as an intermediary that automatically manages the enable signal without requiring external timing coordination. This intermediary mechanism provides reliable signal transmission by preventing glitch transmission through autonomous control, eliminating the need for additional timing signal infrastructure
3Productivity
If supply detection enables driver circuits during slow rising power supply, then circuits are activated, but Vcc level drops causing threshold shift and voltage oscillations
Solution Approach 1:
The patent implements feedback control where the enable signal is continuously adjusted based on the detected Vcc level. When Vcc drops due to loading, the feedback mechanism detects this and prevents further circuit activation or disables affected circuits, thereby maintaining voltage stability and preventing oscillations while maximizing productivity through controlled activation
Solution Approach 2:
The patent employs dynamic control of the enable signal based on real-time voltage detection. The system adapts its behavior by enabling circuits when voltage is sufficient and disabling them when voltage drops, creating a dynamic balance between productivity and stability that prevents threshold shifts and oscillations during power supply variations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively mitigates power supply output glitches during ramp-up by providing hysteresis and attenuating unwanted voltage pulses, preventing false disable signals and oscillations, thus reducing excess current and ensuring stable operation.
Implementation Method 1
a feedback stage field effect transistor; wherein the inverter stage comprises a complimentary pair of transistors... configured and arranged such that a gate lengths of the PMOS and NMOS transistors are different
Data Source
AI summary
This disclosure relates to a power supply detection circuit, including: a first input stage field effect transistor; an inverter stage; and a feedback stage field effect transistor. The inverter stage includes a complimentary pair of transistors that includes an NMOS transistor and a PMOS transistor configured and arranged such that gate lengths of the PMOS and NMOS transistors are different. The disclosure also relates to an integrated circuit including a power supply detection circuit.