Power Detector Circuit DC Offset Calibration
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Solution Overview
Problem
Conventional power detector circuits face challenges in achieving accurate power detection while minimizing power consumption, area usage, and capacitive loading on RF signal paths, often requiring high power and complex circuitry to compensate for DC offsets.
Innovation Solution
The proposed power detector circuits incorporate input, reference, comparison, and error compensation circuitry, including non-linear elements, low pass filters, and digital-to-analog converters, to generate and adjust DC offset calibration signals or gains, thereby compensating for DC offsets without increasing power or area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional power detector circuits use high power consumption and complex circuitry to compensate for DC offsets, then power detection accuracy is improved, but power consumption and device complexity increase
Solution Approach 1:
The patent applies preliminary action by performing DC offset calibration before normal power detection operations. The calibration mode pre-determines correction values that are then applied during normal operation, eliminating the need for continuous complex compensation circuitry and reducing overall power consumption while maintaining accuracy
Solution Approach 2:
The patent changes operational parameters by switching between calibration mode and normal mode. During calibration, specific test signals are applied to determine DC offset characteristics, and these calibrated parameters are then used during normal operation to compensate for offsets without requiring continuous high power consumption
2Measurement precision
If conventional power detector circuits use complex circuitry to compensate for DC offsets, then power detection accuracy is improved, but device complexity increases
Solution Approach 1:
The calibration mode performs preliminary measurement of DC offsets and stores correction values. This preliminary action simplifies the normal mode circuitry because the complex compensation calculations are done in advance during calibration, rather than requiring continuously complex circuitry during operation
Solution Approach 2:
The patent uses a simplified model approach where DC offset characteristics are copied from calibration measurements and applied during normal operation. This allows accurate compensation without implementing complex real-time compensation circuitry, reducing device complexity while maintaining precision
3Measurement precision
If power detector circuits increase power consumption, then accuracy of power detection is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by alternating between calibration mode (low power) and normal detection mode. The calibration is performed periodically or initially to establish correction values, then normal operation uses these pre-determined values with minimal power consumption, avoiding continuous high power consumption while maintaining accuracy
Data Source
AI summary
Embodiments of power detector circuits and related methods to compensate for undesired DC offsets generated within power detector circuits are disclosed. Input signals having input frequencies are received and converted to a magnitude signal, and reference signals are also generated. The magnitude signal may include a DC component proportional to a power of the input signal along with undesired DC offsets. The reference signal may include a DC component proportional to a power of at least one input reference signal along with undesired DC offsets. To compensate for errors introduced by the DC offsets, a DC offset calibration signal or a gain are determined in a calibration mode and then applied in a normal mode to compensate for the DC offsets. For the calibration mode, a difference between the magnitude signal and the reference signal is compared to a threshold value to generate a power detection output signal.