Power Detector Wide Dynamic Range Logarithmic Conversion
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Solution Overview
Problem
Existing power detector circuits in CMOS IC technologies require large chip die area and consume significant current to achieve a linear response to signal power, which is not efficiently addressed by prior art methods.
Innovation Solution
A power detector circuit with wide dynamic range is implemented using a linear voltage-to-voltage detector followed by a logarithmic voltage-to-current-to-voltage converter and an amplification stage, optimized for linearity and minimal offset voltage impact, with temperature compensation through active resistance circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If prior art power detectors use cascaded stages to create piece-wise approximation for linear-in-dB response, then the desired linear response is achieved, but chip die area and current consumption increase significantly
Solution Approach 1:
The patent changes the fundamental operating parameters of the detector by using a logarithmic voltage-to-current converter instead of piece-wise linear approximation. This parameter change transforms the detection mechanism from linear segmentation to logarithmic transformation, achieving linear-in-dB response with fewer components and reduced chip area.
Solution Approach 2:
The patent replaces the mechanical/circuit-based piece-wise approximation approach with a logarithmic conversion mechanism. By substituting the cascaded stage structure with a logarithmic voltage-to-current converter followed by a voltage-to-voltage detector, the system achieves the same linear-in-dB response with significantly reduced complexity and area.
2Measurement precision
If prior art power detectors use cascaded stages for linear response, then the linear-in-dB response is achieved, but current consumption increases
Solution Approach 1:
The patent changes the detection parameter from piece-wise linear voltage stages to logarithmic current conversion. This parameter change reduces the number of active stages required, thereby reducing total current consumption while maintaining linear-in-dB response accuracy.
Solution Approach 2:
The patent substitutes the energy-intensive cascaded voltage stages with a more efficient logarithmic voltage-to-current converter architecture. This substitution reduces power dissipation by eliminating redundant amplification stages while preserving measurement precision.
3Device complexity
If standard voltage-to-voltage detector is used directly, then circuit simplicity is maintained, but offset voltage corrupts the output voltage
Solution Approach 1:
The patent introduces a logarithmic voltage-to-current converter as an intermediary stage between the RF input and the voltage-to-voltage detector. This intermediary transforms the input voltage to current logarithmically, which then feeds the voltage-to-voltage detector, thereby preventing offset voltage corruption while maintaining overall circuit simplicity.
Solution Approach 2:
The patent segments the detection function into two distinct stages: a logarithmic voltage-to-current conversion stage and a voltage-to-voltage detection stage. This segmentation allows each stage to be optimized for its specific function, with the first stage handling the logarithmic transformation and the second stage providing stable voltage output with minimal offset impact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a linear-in-dB response with reduced chip area and current consumption, effectively mitigating temperature sensitivity and offset voltage corruption, thereby enhancing the efficiency and accuracy of power detection.
Implementation Method 1
The current-to-voltage conversion in the voltage-to-current-to-voltage converter is performed logarithmically. This construct generates a desired linear-in-dB response at the output.
Data Source
AI summary
A power detector with wide dynamic range. The power detector includes a linear detector, followed by a voltage-to-current-to-voltage converter, which is then followed by an amplification stage. The current-to-voltage conversion in the converter is performed logarithmically. The power detector generates a desired linear-in-dB response at the output. In this power detector, the distribution of gain along the signal path is optimized in order to preserve linearity, and to minimize the impact of offset voltage inherently present in electronic blocks, which would corrupt the output voltage. Further, the topologies in the sub-blocks are designed to provide wide dynamic range, and to mitigate error sources. Moreover, the temperature sensitivity is designed out by either minimizing temperature variation of an individual block such as the v-i-v detector, or using two sub-blocks in tandem to provide overall temperature compensation. In one aspect, active resistors are used in order to compensate for temperature variations.