Power Device Bottom Source Electrode Design
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Solution Overview
Problem
Existing semiconductor power devices face high power consumption, expensive cup-shaped metal can production, and difficulty in adjusting the gate electrode to match PCB pads due to fixed electrode positions, along with high substrate resistance, which limits the application and efficiency of DC-DC power converter devices.
Innovation Solution
A power device design featuring a bottom source electrode with a lead frame unit, conductive epoxy, and a bridge-shaped metal clip for improved electrical connections and heat dissipation, combined with a wafer level chip scale packaging method to reduce substrate resistance and enable ultra-thin chip production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a cup-shaped metal can is used to package the power device, then heat dissipation performance is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent replaces the expensive cup-shaped metal can with a cost-effective plastic packaging body that achieves sufficient heat dissipation through integrated thermal pathways and exposed bottom electrodes, eliminating the need for costly metal forming processes while maintaining adequate thermal management for power device applications
2Stability of the object's composition
If the source electrode and gate electrode are fixed in the packaging structure, then structural stability is improved, but adaptability to different PCB pad configurations deteriorates
Solution Approach 1:
The patent implements adjustable electrode positions within the packaging structure, allowing the source and gate electrodes to be repositioned to match different PCB pad layouts. This dynamic configuration capability enables the same packaging structure to adapt to various application requirements while maintaining structural integrity through controlled adjustment mechanisms
3Ease of manufacture
If conventional wafer level chip scale packaging is used, then production process is simplified, but substrate resistance remains high
Solution Approach 1:
The patent modifies the substrate structure by changing its geometric parameters and material composition to reduce resistance. This includes optimizing the substrate thickness, doping concentration, and metallization layer configuration to achieve lower on-resistance while maintaining the simplicity of wafer-level packaging processes and ultra-thin chip dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces substrate resistance, enhances heat dissipation, and facilitates easier integration with PCBs by exposing bottom surfaces for improved contact, thereby increasing the efficiency and applicability of semiconductor power devices.
Implementation Method 1
a drain electrode at one side of the MOSFET 10 is connected to the bottom of the interior space of the cup-shaped metal can 12 through a layer of conductive epoxy 14
Implementation Method 2
improving the electrical connection and heat dissipation performance of the devices
Implementation Method 3
enhances heat dissipation
Implementation Method 4
heat dissipation performance
Data Source
AI summary
A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.