Semiconductor Power Device Bump Bonding Current Distribution
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Solution Overview
Problem
Semiconductor power devices face challenges in reducing processing steps and manufacturing costs due to metal deposition thickness limitations, which necessitate extensive processing for backside contacts, increasing series resistance and costs.
Innovation Solution
The use of a bump or loaf array to distribute current between semiconductor power device elements and a thicker lead-frame eliminates the need for a separate backside contact, allowing for flip-chip attachment and reducing processing steps and costs, while enabling lower resistance substrates and eliminating the epitaxial silicon growth step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If backside contact is used for power elements, then current carrying capability is improved, but processing complexity and manufacturing cost increase due to extensive processing steps required to eliminate series resistance
Solution Approach 1:
The patent inverts the conventional approach by placing power element contacts (source and drain) on the front side of the semiconductor die rather than the back side. These front-side contacts are then electrically connected to the lead-frame through conductive bumps, eliminating the need for extensive backside processing while maintaining current carrying capability.
Solution Approach 2:
The patent introduces conductive bumps as intermediary elements that connect the front-side power element contacts to the lead-frame. These bumps serve as mediators that enable current flow without requiring backside contacts, thereby simplifying processing while maintaining electrical performance.
2Ease of manufacture
If metal deposition thickness is limited, then fabrication cost is reduced, but current carrying capability deteriorates due to insufficient conductor thickness
Solution Approach 1:
The patent transitions from planar metal deposition to three-dimensional bump structures. By forming conductive bumps with vertical height, the current carrying capability is enhanced without increasing the planar deposition area or metal thickness, thus maintaining cost-effectiveness while improving electrical performance.
Solution Approach 2:
The patent changes the geometric parameters of the conductors by forming bumps with controlled height and cross-sectional area. This allows optimization of current carrying capability through vertical dimension while keeping the metal deposition thickness within acceptable fabrication limits.
3Reliability
If extensive processing is performed to eliminate series resistance, then electrical performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the power element contacts from the back side of the die and relocates them to the front side. This eliminates the need for extensive backside processing steps required to reduce series resistance, thereby simplifying manufacturing while maintaining electrical performance through the bump connection architecture.
4Reliability
If separate backside contact is used, then current distribution is improved, but device form-factor increases due to additional processing layers
Solution Approach 1:
The patent merges the functions of front-side contacts and backside contacts by implementing all power element contacts (source and drain) on the front side only. The conductive bumps provide the necessary electrical connection to the lead-frame, eliminating the need for separate backside contact structures and reducing overall device form-factor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in lower processing and manufacturing costs, a smaller form-factor, and the ability to integrate source and drain contacts on one face of the die, facilitating wafer-level-chip-scale-package solutions and interconnection of multiple power-FETs in a single package.
Implementation Method 1
using bump bonding to distribute current flow on a semiconductor power device
Data Source
Figure 1
Figure 2A~2B
Figure 3
AI summary
A semiconductor power chip may have a semiconductor die (102), having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element (110, G), a plurality of second contact elements (S) and a plurality of third contact elements (D) arranged on top of the semiconductor die;a plurality of ball bumps (106, 108) or a loaf bump disposed on each of the plurality of second elements and the plurality of third elements; and at least one ball bump (104) or loaf on the at least one first contact element.