Power Device Integration on Common Substrate
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Solution Overview
Problem
Current power management systems for portable electronic devices face challenges in miniaturization and cost due to the allocation of large die area to power switches, leading to high product costs and limitations in high-frequency applications, especially when device power consumption exceeds a few watts.
Innovation Solution
The integration of power devices, including drivers and switches, on a common silicon substrate using BiCMOS IC fabrication technology with silicon-on-insulator (SOI) substrates and dielectric lateral isolation, allowing for a monolithic integration of various power components and reducing parasitic impedances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If power switches are implemented using MOSFET devices with standard fabrication processes, then the manufacturing process is simple and cost-effective, but the die area allocated to power switches becomes large, leading to high product costs
Solution Approach 1:
The patent changes the fabrication parameters by introducing a specialized process that forms lightly-doped drain extensions and specific well structures, allowing power switches to achieve higher voltage handling capability in a reduced area while maintaining manufacturing feasibility through modified standard steps
Solution Approach 2:
The patent applies local quality by creating regions with different doping concentrations (lightly-doped drain extensions, heavily-doped source/drain regions) and structures (buried wells, isolation oxide) in specific locations to optimize the power switch performance and reduce the required die area
2Volume of moving object
If power management components are integrated into a single IC chip, then device miniaturization is achieved, but the integration of high-power switches with control circuitry increases fabrication complexity and cost
Solution Approach 1:
The patent segments the power switch structure into distinct functional regions (source, drain, gate, buried well, isolation oxide) that can be formed using separate fabrication steps, allowing the high-power components to be integrated with control circuitry while managing fabrication complexity through modular processing
Solution Approach 2:
The patent uses composite material structures combining silicon-on-insulator substrates with selectively-doped regions and oxide layers to create power switches that can be integrated with standard CMOS control circuitry, balancing miniaturization with fabrication complexity
3Volume of stationary object
If the switching frequency is increased to reduce filter component size, then the volume and cost of filter components decrease, but hot carrier injection issues and reliability problems increase
Solution Approach 1:
The patent implements beforehand cushioning by forming lightly-doped drain extensions and buried wells before the final device operation, which preemptively reduce electric field peaks and prevent hot carrier injection damage during high-frequency switching, thereby maintaining reliability at increased switching frequencies
Solution Approach 2:
The patent changes the electrical parameters by modifying the doping profiles and structural dimensions to reduce peak electric fields, enabling the device to operate at higher frequencies (up to 5 MHz) without suffering from hot carrier injection reliability issues
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a cost-effective, high-frequency power management solution with reduced volume and cost of filter components, supporting a power range of 3 watts to 30 watts and increasing switching frequency from 1.5 MHz to 5 MHz, while maintaining reliability and minimizing hot carrier injection issues.
Implementation Method 1
The clamping diode is operative to locate a breakdown avalanche region between the buried well and the first terminal in the semiconductor structure
Data Source
AI summary
A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.