Power Device Layout Design Reducing Parasitic Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing power device layout designs for high-voltage and high-current applications face challenges in reducing parasitic resistance and increasing area utilization while maintaining reliability, often requiring multiple metal layers and increasing process costs.
Innovation Solution
A layout design method that routes non-top metal and top metal layers in alternating directions, forming a criss-cross structure with direct connections between layers, reducing the number of metal layers to three, and arranging pads within the top metal region to enhance contact area and minimize parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If stack-up wiring of two layers of metal is used to increase metal overcurrent capability, then the overcurrent capability is improved, but the parasitic resistance cannot be reduced effectively and process costs significantly increase
Solution Approach 1:
The patent transitions from traditional vertical stack-up wiring to a two-dimensional criss-cross layout where metal wires are routed in alternating directions (first direction and vertical direction) across multiple layers. This dimensional reorganization allows parallel current paths without increasing vertical layer count, thereby reducing parasitic resistance while maintaining overcurrent capability.
Solution Approach 2:
The patent segments the metal wiring into multiple independent paths by routing wires in alternating directions across different layers. Each layer contains wires oriented in specific directions, creating segmented current paths that reduce parasitic resistance through parallel conduction while avoiding the need for additional stack-up layers.
2Power
If stack-up wiring of two layers of metal is used to increase metal overcurrent capability, then the overcurrent capability is improved, but the process costs significantly increase
Solution Approach 1:
The patent achieves overcurrent capability through two-dimensional spatial arrangement rather than vertical stacking. By routing metal wires in alternating directions across layers and using criss-cross connections, the design achieves high current capacity without requiring additional metal layers, thereby reducing manufacturing complexity and cost.
3Power
If large gate width parallel design and large-area metal wiring design are used to meet high current and high voltage application demands, then the overcurrent capability is improved, but the area utilization is reduced
Solution Approach 1:
The patent utilizes vertical and diagonal routing directions to pack metal wires more efficiently within the available die area. The criss-cross arrangement allows multiple current paths to share the same planar space vertically, increasing area utilization while maintaining high overcurrent capability through parallel conduction paths.
Data Source
AI summary
The disclosure discloses a layout design method, chip and terminal of power device, wherein the non-top metal layout design: the metal is routed along the first direction and several metal wires that fully occupy the available area of the die unit are thereby obtained, and the wiring properties of the metal wires are sequentially changed at intervals, making the source ends and the drain ends of the device are alternately distributed at intervals, and the metal routing in two or more layers of non-top metal are arranged vertically; the top metal layout design: the source end region and drain end region in the top metal are formed into sheets independently and the pad is arranged in the top metal region; eventually realize the interconnection of metal layers and complete the layout design. The disclosure adopts a criss-cross design between non-top metals, thereby the device has a smaller parasitic resistance value; the removal of the stack-up design can reduce the metal layer design and save the cost; the source end and drain end regions in the top metal are designed into sheets to ensure the adequacy of the interconnection between the metal layers and further improve the reliability of the device.