Multi-Layer Contact Stack for Thick Power Semiconductor Die Attach
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Solution Overview
Problem
The high cost and limited thickness of AuSn diffusion solder die attach materials for power semiconductor chips pose challenges in the die attach process, particularly due to high temperature cycling and storage reliability requirements.
Innovation Solution
A layer system comprising a semiconductor substrate, an electrical contact layer, a functional layer, an adhesion layer, and a solder layer is used, where the solder layer is a noble metal-free alloy, allowing for thicker application and reduced stress through isothermal solidification, and intermetallic phases are formed between the adhesion layer and the solder layer, enabling easier die attach and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If AuSn diffusion solder die attach material is used, then high temperature cycling and storage reliability is achieved, but the solder layer thickness is limited and costs are high
Solution Approach 1:
The patent segments the soldering process into two distinct stages: a first soldering step that forms an initial solder layer with specific intermetallic compound formation, and a second soldering step that adds additional solder material. This segmentation allows the solder layer to achieve both the reliability benefits of controlled intermetallic formation and the thickness benefits of cumulative material deposition, resolving the contradiction between reliability and solder layer thickness.
2Reliability
If AuSn diffusion solder die attach material is used, then high temperature cycling and storage reliability is achieved, but costs are high
Solution Approach 1:
The patent replaces the expensive AuSn (gold-tin) diffusion solder material with a cost-effective Sn-Ag-Cu (tin-silver-copper) alloy system. This substitution maintains the essential functionality of forming reliable intermetallic compounds during soldering while dramatically reducing material costs. The two-step soldering process ensures that the cheaper alternative achieves the same reliability performance as the expensive AuSn material.
3Quantity of substance
If noble metal-free solder layer is used, then cost is reduced and thicker application is enabled, but stress management becomes challenging
Solution Approach 1:
The patent utilizes phase transitions during the two-step soldering process to manage stress. The first soldering step creates a controlled intermetallic compound layer that acts as a stress buffer, and the second soldering step adds material that undergoes controlled solidification. This phased approach to material deposition and phase transformation enables the thicker noble metal-free solder layer to accommodate thermal and mechanical stress effectively.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for a more cost-effective and reliable die attach process with reduced stress and improved reliability by using a noble metal-free solder layer, enabling thicker application and lower soldering temperatures, thus addressing the limitations of AuSn diffusion solder.
Implementation Method 1
allowing for thicker application and reduced stress through isothermal solidification
Implementation Method 2
intermetallic phases are formed between the adhesion layer and the solder layer
Data Source
AI summary
An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.