Power Semiconductor Die Embedding for Thermal Management
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Solution Overview
Problem
Conventional power semiconductor device packaging methods, such as the 'chip & wire' and 'flip-chip' approaches, face challenges in efficiently managing heat dissipation and reducing package size while maintaining electrical connectivity and mechanical support for high-power semiconductor dies.
Innovation Solution
The method involves embedding a power semiconductor die within an insulating core layer with a main cavity, using a conductive material on the cavity sidewall for electrical connections and an insulation structure for mechanical support, allowing all terminal interfaces to be on the package footprint side while utilizing the top side for heat dissipation, thereby eliminating the need for through holes and enhancing power density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional chip & wire or flip-chip approaches are used, then electrical connectivity is maintained, but heat dissipation efficiency is reduced and package size is increased
Solution Approach 1:
The patent inverts the conventional packaging approach by embedding the die within the core layer rather than mounting it on the surface. The die is positioned with its backside facing the package top side, allowing heat to dissipate directly upward through the package structure, while electrical connections are established through the cavity sidewall from the side, eliminating the need for through-holes and bonding wires that increase package size.
Solution Approach 2:
The patent transitions from conventional two-dimensional surface mounting to three-dimensional embedding. The die is positioned within a cavity in the core layer, utilizing the vertical dimension for heat dissipation while electrical connections are made through the lateral cavity sidewall. This spatial reconfiguration optimizes both thermal management and electrical connectivity without increasing package footprint.
2Reliability
If through holes are used for electrical connections, then connectivity is achieved, but manufacturing complexity and package size increase
Solution Approach 1:
The patent extracts the electrical connection function from the conventional through-hole approach. Instead of creating holes through the entire core layer thickness, the connection is established through a cavity sidewall that is formed and filled with conductive material. This eliminates the need for deep through-holes and associated manufacturing steps, reducing manufacturing complexity while maintaining reliable electrical connectivity.
3Reliability
If bonding wires are used for electrical connections, then connectivity is achieved, but mechanical reliability and power handling capability are reduced
Solution Approach 1:
The patent replaces the mechanical bonding wire system with a direct conductive material connection through the cavity sidewall. This substitution eliminates the mechanical weaknesses of wire bonds, providing a more robust electrical connection that can handle higher power levels and offers superior mechanical reliability under thermal and electrical stress.
4Temperature
If die is mounted on surface with bonding wires, then electrical connections are established, but heat dissipation path is lengthened and efficiency reduced
Solution Approach 1:
The patent inverts the conventional mounting orientation by positioning the die backside toward the package top side within the cavity. This configuration creates a direct heat dissipation path from the die through the package structure, eliminating the need for heat to travel through bonding wires and extended mounting structures, thereby significantly reducing the heat dissipation path length and improving thermal efficiency.
Data Source
AI summary
A power semiconductor device package includes a power semiconductor die having a first load terminal at a die frontside and a second load terminal at a die backside. The package has a package top side, a package footprint side, and a first terminal interface and a second terminal interface arranged at the package footprint side. The first terminal interface is electrically connected with the first load terminal. The die is disposed in a main cavity of an insulating core layer. A conductive material is provided at a cavity sidewall of the main cavity, and an insulation structure is provided in the main cavity. The insulation structure embeds the die, with the die backside facing the package top side. An electrical connection provided between the second load terminal and the second terminal interface is formed by at least the conductive material at the cavity sidewall.