Power Distribution Grid IR Drop Reduction
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Solution Overview
Problem
Conventional circuit designs face challenges in minimizing voltage resistance drops due to higher resistance in lower metal and via layers, which affects the power distribution network's efficiency, especially in sub-64 nm metal pitched process technologies.
Innovation Solution
Implementing a local micro power grid above the power switch cell with additional horizontal and vertical metal layer routing and redundant vias to reduce current-resistance (IR) drops, and using a global power distribution grid with stacked metal and via layers to optimize power distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If lower metal and via layers are used for standard cell grid and totem structures, then routing density increases, but resistance increases significantly
Solution Approach 1:
The patent transitions from relying solely on lower metal layers (2D planar routing) to utilizing upper metal layers (3D vertical routing) to reduce resistance. By stacking metal layers vertically and using vias to connect them, the power distribution network exploits the third dimension to create lower-resistance paths while maintaining routing density in the lower layers.
Solution Approach 2:
The patent creates a composite power distribution structure by combining multiple metal layers with different resistance characteristics. Lower metal layers provide dense routing, while upper metal layers provide low-resistance power delivery paths. The combination of metals and vias forms a composite structure that leverages the advantages of each layer.
2Productivity
If via layers are increased to connect power rails to global metal grid, then power distribution efficiency improves, but via resistance becomes significantly higher than metal layer resistance
Solution Approach 1:
The patent merges multiple power distribution paths by combining horizontal power rails in lower metal layers with vertical vias and upper metal layer global grids. Instead of relying on a single high-resistance via path, the invention creates parallel paths through multiple vias and combines them with low-resistance upper metal layer routing, effectively merging the advantages of both vertical and horizontal power distribution.
Solution Approach 2:
The upper metal layers act as an intermediary between the lower metal layer power rails and the global power distribution network. Rather than directly connecting lower power rails to distant global grid points through high-resistance vias, the upper metal layers provide a low-resistance intermediate routing path that spans across the chip, reducing the effective resistance of the overall power delivery path.
3Reliability
If resistance of lower metal layers is reduced by increasing metal width, then IR drop decreases, but routing flexibility and pitch constraints are violated
Solution Approach 1:
The patent resolves the conflict between reducing resistance and maintaining routing flexibility by moving the low-resistance power delivery function to upper metal layers. This allows lower metal layers to maintain their fine pitch and high routing density for signal connections, while upper layers provide wide, low-resistance power paths. The separation of functions across vertical dimensions preserves both IR drop performance and cell placement flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces resistance and improves power distribution efficiency, allowing for flexible cell placement and high efficiency in power switches, particularly in memory applications.
Implementation Method 1
global distribution wires are typically routed in upper metal layers. A standard cell's power rails are typically routed horizontally, and the power rails are connected to upper global metal grid layers through stacked metal and via layers, or totems.
Implementation Method 2
resistance of lower metal and via layers that are used for a standard cell grid and totem structures are significantly higher than the upper metal grid layers. Generally, resistance increases when descending into a standard cell stack such that lower metal layers are more resistive than upper metal layers
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit having a power gate cell and a first power distribution grid. The integrated circuit may include a second power distribution grid aligned with and disposed above the power gate cell. The second power distribution grid may be disposed between the power gate cell and the first power distribution grid.