Multi-Power-Domain Bridge with Scoreboarding for Memory Throughput
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Solution Overview
Problem
In multi-core coherent systems, the heterogeneity of cache structures and memory access types across different processor components leads to increased CPU stall overhead and reduced memory throughput, making it challenging to maintain data consistency and maximize shared memory bandwidth.
Innovation Solution
A processing system with a bridge that includes interface circuitry for address conversion, buffers for clock domain transition, and address hazarding circuitry for scoreboard management, enabling efficient memory access and response handling across different clock domains and cache structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the interconnect handles memory accesses in a serial fashion to guarantee data consistency, then data coherency is maintained, but memory throughput and bandwidth are reduced
Solution Approach 1:
The interconnect is divided into multiple parallel channels or lanes that can simultaneously handle different memory access transactions. Each channel maintains independent arbitration and coherency management, allowing multiple masters to access different slaves concurrently without serializing all transactions through a single bottleneck, thus maintaining data consistency while increasing overall memory throughput
Solution Approach 2:
A coherency manager or arbitration unit acts as an intermediary that receives memory access requests from multiple masters, arbitrates them based on coherency protocols and priority, and routes them through appropriate parallel paths to slaves. This mediator enables concurrent access by intelligently managing transaction ordering and coherency states without requiring complete serialization of all memory operations
2Loss of time
If CPU cache allocate accesses request critical line first return to un-stall CPU, then CPU stall overhead is reduced, but other CPU's stall overhead increases and shared memory throughput decreases
Solution Approach 1:
The system implements a critical line first return mechanism where memory allocate accesses are pre-tagged with priority indicators. When multiple allocate requests are pending, the memory subsystem proactively identifies and completes critical line transfers first based on CPU stall state information, allowing the requesting CPU to un-stall sooner without completely blocking other memory operations
Solution Approach 2:
The memory arbitration and transaction handling is made dynamic by continuously monitoring CPU stall states and adjusting the priority of memory allocate requests in real-time. The system can dynamically switch between serving critical lines first and maintaining fair sharing based on current system conditions, optimizing the balance between reducing CPU stall overhead and maintaining overall memory throughput
3Adaptability or versatility
If different components have different cache structures and access types, then system functionality and versatility are improved, but access bottleneck and interconnect complexity increase
Solution Approach 1:
The interconnect is designed with a universal arbitration and routing fabric that can handle multiple types of memory access transactions (read, write, allocate, invalidate) from diverse masters with different cache structures. The coherency manager provides multi-functional support for various cache protocols and access types through a unified interface, reducing the need for separate specialized interconnect paths for each component type
Data Source
AI summary
Techniques for accessing data, comprising receiving a first memory request associated with a first clock domain, converting a first memory address of the first memory request from a first memory address format associated with the first clock domain to a second memory address format associated with the second clock domain, transitioning the first memory request to a second clock domain, creating a first scoreboard entry associated with the first memory request, transmitting the first memory request to a memory based on the converted first memory address, receiving a first response to the first memory request, transitioning the first response to the second clock domain and clearing the first scoreboard entry based on the received response.