Switchable Power-Domain Bus Assignment for Scalable IP Blocks
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Solution Overview
Problem
Existing power-domain architectures, such as flat and stacked designs, face challenges in scalability and power consumption due to fixed level shifter and voltage rail assignments, which become inefficient as the number of IP blocks and power-domains increases, leading to significant silicon area and power overhead.
Innovation Solution
A bus-based power-domain assignment system that allows dynamic configuration of power-domains through a switchable bus architecture with merged level shifter and control logic, enabling finer control over load balancing and reducing the need for dedicated level shifters and voltage rails, thereby minimizing chip area, power consumption, and control overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed level shifter and voltage rail assignments are used in traditional power-domain architectures, then power domains can be established, but silicon area and power overhead increase significantly as the number of IP blocks and power-domains increases
Solution Approach 1:
The level shifter is designed to serve multiple power-domain buses universally. Instead of having dedicated level shifters for each bus pair, a single level shifter can be dynamically assigned to couple any top power-domain bus with any bottom power-domain bus through the switch fabric, making the level shifter multi-functional and reducing the total number of level shifters required
Solution Approach 2:
The power-domain architecture is segmented into top and bottom power domains with independent voltage rails, allowing flexible assignment of IP blocks to different domains. The switch fabric is also segmented into multiple switches that can be independently configured to create different power-domain bus assignments, enabling scalable configuration as the number of IP blocks increases
2Adaptability or versatility
If fixed level shifter and voltage rail assignments are used in traditional power-domain architectures, then power domains can be established, but power consumption increases due to inability to dynamically optimize power distribution
Solution Approach 1:
The architecture introduces dynamic reconfigurability where the switch fabric can be programmed at runtime to assign different IP blocks to different power domains based on power consumption requirements. This dynamic assignment allows the system to optimize power distribution adaptively, switching between different power-domain configurations as workload and power conditions change
Solution Approach 2:
The system changes the voltage domain parameters dynamically by assigning IP blocks to different voltage rails (top or bottom power domains) based on their power consumption characteristics. This parameter change enables fine-grained power control, where the voltage supply to different IP blocks can be adjusted independently to minimize overall power overhead
3Reliability
If dedicated level shifters and voltage rails are assigned to each IP block, then power-domain isolation is achieved, but control overhead and device complexity increase
Solution Approach 1:
Multiple switch control functions are merged into a unified switch fabric controlled by a single controller. The controller manages the entire power-domain assignment by programming the switches in the fabric, consolidating control logic and reducing the number of independent control mechanisms needed while maintaining proper power-domain isolation
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 2C
AI summary
Example apparatus for power-domain assignment, having: a first bus-to-switch interface (302); a second bus-to-switch interface (304); a first power-domain bus (306), coupled to the first bus-to-switch interface (302); a second power-domain bus (312), coupled to the second bus-to-switch interface (304). A set of I/O signal level shifters (318), coupled between the first and second power-domain buses (306, 312); a switch (320) including, a set of IP block power coupling outputs (322, 324); a set of IP block I/O signal paths (326); and a selection signal input (328). The switch (320) is coupled to the first and second bus-to-switch interfaces. Wherein, in response to receiving a first signal on the selection signal input, the switch is configured to couple the first power-domain bus to the set of IP block power coupling outputs; and wherein, in response to receiving a second signal on the selection signal input, the switch is configured to couple the second power-domain bus to the set of IP block power coupling outputs.