Power Domain Isolation Interface with Latch-Held Logic States

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Solution Overview

Problem

Existing power domain interfaces in semiconductor circuits face challenges with maintaining low power consumption due to static leakage current and indeterminate states when shutting down power supplies, particularly in interfacing between different voltage domains.

Innovation Solution

A power domain isolation interface system that includes a level shifter and a latch, where the latch holds the input state and the level shifter is disabled to prevent leakage, allowing for reliable state retention and power management between power domains.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If power supply is disabled to reduce dynamic power consumption, then power consumption is reduced, but static leakage current and indeterminate states occur at interface logic

Engineering Contradiction:
Improvepower consumptionVSAvoidinterface logic stability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The interface logic is segmented into two separate domains: a first domain connected to the first power supply and a second domain connected to the second power supply. This segmentation allows each domain to be independently powered and controlled, enabling the interface logic to maintain stability even when one power supply is disabled. The level shifter acts as the boundary between these segmented domains, ensuring proper signal translation and isolation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A level shifter is introduced as an intermediary component between the two power domains. The level shifter translates signals from the voltage level of the first power supply to the voltage level of the second power supply, enabling communication between domains while maintaining electrical isolation. This intermediary prevents direct coupling between power domains, eliminating leakage current paths and indeterminate states at the interface.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Use of energy by moving object

If clock gating is used to disable unused sections, then dynamic power consumption is reduced, but static leakage current remains significant

Engineering Contradiction:
Improvedynamic power consumptionVSAvoidstatic leakage current
Core Design Contradiction:
Use of energy by moving objectVSLoss of energy

Solution Approach 1:

The patent applies preliminary action by disabling the power supply to the first power domain before or during the shutdown of the associated circuit section. By removing the power supply voltage entirely (rather than just gating the clock), the circuit is placed in a true low-power state where both dynamic and static power consumption are minimized. The level shifter and second power domain remain active to maintain interface functionality.

Inventive Principle:
Principle #10Preliminary action

3Use of energy by moving object

If multiple supply voltages are used to power different sections, then power consumption is optimized, but interface logic between power domains becomes complex

Engineering Contradiction:
Improvepower consumptionVSAvoidinterface logic complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The level shifter is designed as a universal interface component that handles multiple functions: voltage level translation, power domain isolation, and signal direction control. By consolidating these functions into a single standardized interface structure, the patent reduces overall system complexity despite using multiple supply voltages. The same level shifter architecture can be reused across different power domain interfaces within the system.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7982498B1System and method for power domain isolation
Publication Date: 2011.07.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US7982498B1 patent drawing
  • US7982498B1 patent drawing
  • US7982498B1 patent drawing

AI summary

In one embodiment, a power domain isolation interface is disclosed. The interface has a level shifter having a signal input coupled to a first power domain and a memory element. The memory element has a signal input coupled to an output of the level shifter, an output coupled to a second power domain, and a hold enable input, wherein the memory element is configured to hold an input state when the hold enable input becomes asserted.