Power Domain Region Detection for Nested Multi-Power IC Layouts
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Solution Overview
Problem
Existing electronic design automation (EDA) place-and-route tools struggle to efficiently route power to pre-gated logic instances in integrated circuit designs, especially when the relative area of pre-gated domain logic increases, leading to unrouteable designs and unusable layouts due to their lack of power grid awareness.
Innovation Solution
A method that involves scanning the initial placement of domain instances to identify preselected power specifications, applying heuristics to form observation areas, and selectively merging instances to create contiguous regions with predetermined power specifications, thereby revising the placement of domain instances to facilitate power routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If EDA place-and-route tools place pre-gated domain instances based on timing and congestion alone without power grid awareness, then placement flexibility is improved, but power routing feasibility deteriorates
Solution Approach 1:
The patent performs power domain region detection during the placement phase, before routing is completed. It scans the initial placement to identify regions with high concentration of pre-gated instances and determines power domain boundaries in advance, allowing the routing process to proceed with knowledge of power requirements rather than discovering conflicts later
Solution Approach 2:
The patent introduces a power domain region detection mechanism that acts as an intermediary between the placement tool and the routing tool. This intermediary analyzes the placement, identifies power domain regions, and provides guidance information to the routing process, enabling coordinated power-aware routing without requiring fundamental changes to either placement or routing algorithms
2Productivity
If clustering technique is used to group pre-gated logic instances, then power routing efficiency is improved for small amounts of logic, but design routability deteriorates when large numbers of cells are involved
Solution Approach 1:
The patent segments the integrated circuit design into multiple power domain regions based on the spatial distribution of pre-gated instances. Instead of creating a single large cluster, it divides the design into contiguous regions where each region can be independently routed with appropriate power supply assignments, preventing the creation of unrouteable centralized power islands
Solution Approach 2:
The patent applies different power domain assignments to different regions of the design based on local concentrations of pre-gated instances. Rather than applying a uniform clustering approach throughout the entire design, it identifies specific regions where pre-gated instances are concentrated and applies power domain boundaries locally to those regions, maintaining routing flexibility in other areas
3Speed
If pre-gated domain instances are scattered throughout the integrated circuit tile, then placement optimization based on timing is improved, but power supply accessibility deteriorates
Solution Approach 1:
The patent addresses the scattering problem by introducing a spatial dimension analysis to the placement evaluation. It scans the placement to identify regions where pre-gated instances are concentrated and creates power domain boundaries that respect both the timing-optimized scattered placement and the power supply network geometry, effectively adding a power-aware dimension to the placement criteria
Data Source
AI summary
A non-transitory computer-readable medium includes instructions that, when provided to and executed by a processor, cause the processor to receive a first placement of domain instances of an integrated circuit layout provided as a tile having a group of multiple power domain modules. The first placement of domain instances is scanned to identify instances associated with a preselected power specification. A heuristic is applied to the first placement of domain instances to form an observation area. The heuristic demarcates select instances to form the observation area. Each instance associated with the preselected power specification is identified in the observation area. A contiguous region of instances is formed from the select instances in the observation area. The first placement of domain instances in the integrated circuit layout is modified to provided revised placement for instances associated with the contiguous region of instances.