Power-Down Buffer Control to Prevent Power Gating Errors
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Solution Overview
Problem
Semiconductor devices face challenges in preventing power gating errors when transitioning from power-down mode to active mode due to insufficient wait time, leading to floating currents and abnormal operations.
Innovation Solution
A semiconductor device with a select control circuit that transitions the logic levels of select signals at specific edges of a chip select signal to control the power gating circuit, ensuring the virtual power and ground voltage lines are not in a floating state before entering the active mode, thereby preventing power gating errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the power gating circuit is turned on immediately when transitioning from power-down mode to active mode, then the operation speed is improved, but power gating errors occur due to floating currents
Solution Approach 1:
The patent applies preliminary action by transitioning the logic level of the second select signal (controlling the power gating circuit) before transitioning the logic level of the first select signal (controlling buffer circuits). This ensures the power gating circuit is activated in advance, allowing virtual power and ground voltage lines to stabilize before the buffer circuits are enabled, thereby preventing power gating errors while maintaining fast operation speed.
2Reliability
If the wait time for power gating circuit activation is extended to prevent floating currents, then power gating stability is improved, but operation speed decreases
Solution Approach 1:
The patent eliminates the need for extended wait time by performing the power gating circuit activation as a preliminary action before the buffer circuits are enabled. The sequential transition of select signals ensures proper activation timing without requiring additional delay, thus maintaining both stability and speed.
3Reliability
If the logic level transition sequence is changed to activate power gating circuit first, then power gating errors are prevented, but control complexity increases
Solution Approach 1:
The patent implements preliminary action through a structured control method where the select control circuit transitions logic levels in a specific sequence. The second select signal (for power gating) is transitioned at the first edge of the chip select signal, while the first select signal (for buffers) is transitioned at the second edge. This systematic approach prevents power gating errors while maintaining clear and manageable control logic.
Data Source
AI summary
A semiconductor device includes: a first buffer circuit configured to receive a chip select signal in a power-down mode in response to a first select signal, a second buffer circuit configured to receive the chip select signal in an active mode in response to the first select signal, a power supply circuit configured to supply external power to a plurality of logic elements in the active mode in response to a second select signal, and not supply the external power to the plurality of logic elements in the power-down mode, and a select control circuit configured to transition a logic level of the second select signal at a first edge of a first chip select signal in the power-down mode, and then transition a logic level of the first select signal at a following second edge of the first chip select signal to exit from the power-down mode and enter the active mode.