Power-Down Clock Control Circuit Using Active-Mode Signals
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Solution Overview
Problem
Conventional semiconductor memory devices require a complex power-down mode control circuit with numerous D flip-flops and multiplexers, leading to increased area occupation and power consumption due to the need for counting various signals to manage clock enable signals during active mode operations.
Innovation Solution
A simplified power-down mode control circuit that uses a combination of buffer units, latch units, and clock enable generation circuits to generate control signals for disabling internal clocks during power-down mode entry, reducing the need for multiple D flip-flops and multiplexers by leveraging control signals from active mode operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complex power-down mode control circuit with numerous D flip-flops and multiplexers is used to count various signals during active mode operations, then the clock enable signals can be managed accurately, but the area occupation and power consumption increase
Solution Approach 1:
The patent extracts the essential control function from the complex signal counting mechanism. Instead of using multiple D flip-flops and multiplexers to count various signals, the invention uses a simplified control circuit that directly responds to the active mode operation control signal to generate the clock enable signal for power-down mode entry, removing unnecessary counting components while maintaining accurate clock control
Solution Approach 2:
The patent makes the active mode operation control signal serve multiple functions. This single signal is used both to control the active mode operation and to trigger the power-down mode entry sequence, eliminating the need for separate signal counting circuits and reducing the overall control circuit complexity
2Reliability
If a complex power-down mode control circuit with numerous D flip-flops and multiplexers is used to count various signals during active mode operations, then the clock enable signals can be managed accurately, but the power consumption increases
Solution Approach 1:
The patent removes the power-consuming D flip-flops and multiplexers from the control circuit. The simplified design uses only essential buffering and signal generation components, dramatically reducing the static and dynamic power consumption of the control circuit while maintaining reliable clock enable signal management
Solution Approach 2:
The control circuit is designed to be self-regulating, where the active mode operation control signal automatically triggers the power-down mode entry sequence without requiring additional active counting components. This self-service mechanism eliminates continuous power consumption associated with signal counting and state machine operation
3Adaptability or versatility
If numerous D flip-flops and multiplexers are used in the power-down mode control circuit, then various signals can be counted and managed, but the control circuit configuration becomes complex
Solution Approach 1:
The patent extracts only the essential control function needed for power-down mode entry, removing the complex signal counting capability implemented with numerous D flip-flops and multiplexers. The simplified circuit maintains adaptability by directly responding to the active mode operation control signal without requiring multiple counting stages
Solution Approach 2:
Instead of using a complex counting approach to determine when to enter power-down mode, the patent inverts the approach by using the active mode operation control signal itself as the trigger. This reversal simplifies the control logic from a multi-stage counting and decision process to a direct signal-responsive mechanism
Data Source
AI summary
A power-down control circuit utilizes the control signals employed in an active mode operation to operate when a power-down mode entry command is received during an active mode operation. The circuit is simplified requiring less area for devising the control circuit while lowering power consumption. The power-down control circuit in a semiconductor memory device includes at least a clock enable buffer unit, an external clock buffer unit, a latch unit, a control circuit for controlling internally operating clocks employed in active mode operation by using a control signal used in the active mode operation when a power-down mode entry command is received during the active mode operation, and a clock enable generation circuit for outputting clock enable signals for enabling entry to the power-down mode by using the clock control signals, when the external clock pulse signal is low level.