Power-Down Controller for Dynamic Logic Block Power Management

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Solution Overview

Problem

Embedded DSP solutions face challenges in minimizing power dissipation to prolong battery life and reduce thermal issues, as existing technologies lack effective mechanisms for power-saving during periods of inactivity.

Innovation Solution

The Generalized Embedded Megamodule (GEM) with the embedded Joule CPU employs a combination of hardware and software to trigger a low-power state during processor IDLE periods, using a power-down controller to power down the CPU and associated memories, and wake them on demand for memory access or emulation commands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the processor and memory remain in active state to ensure immediate response to system events, then system responsiveness is improved, but power consumption increases

Engineering Contradiction:

Improvesystem responsivenessVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The system dynamically transitions between active and low-power states based on processor activity. The power-down controller monitors processor state and automatically powers down memory and logic blocks when the processor enters idle state, then quickly restores them when activity is detected, optimizing the balance between responsiveness and power consumption

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system prepares for low-power operation by detecting idle states and proactively transitioning to power-down mode before significant power consumption occurs. The power-down controller anticipates the need for power savings by monitoring processor activity and initiating the power-down sequence in advance

Inventive Principle:

Principle #10Preliminary action

2Use of energy by moving object

If the processor enters low-power state during idle periods to reduce power dissipation, then power consumption is reduced, but system response time increases

Engineering Contradiction:

Improvepower dissipationVSAvoidsystem response time

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The system minimizes the time spent in transition states by rapidly switching between active and low-power modes. When the processor enters idle state, the power-down controller quickly powers down memory and logic blocks, and when activity is detected, the system rapidly restores functionality, reducing the time penalty associated with state transitions

Inventive Principle:

Principle #21Skipping (Rushing through)

3Use of energy by moving object

If power-down control logic is added to manage low-power states, then power savings are improved, but device complexity increases

Engineering Contradiction:

Improvepower savingsVSAvoidcontrol logic complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The power-down controller operates autonomously by monitoring processor idle state and automatically controlling the power-down of memory and logic blocks without requiring complex external control logic. The system serves itself by having the processor's own idle state signal trigger the power management sequence, reducing the need for additional complex control mechanisms

Inventive Principle:

Principle #25Self-service

Data Source

PatentUSRE46193E1Distributed power control for controlling power consumption based on detected activity of logic blocks

Publication Date: 2016.11.01 TEXAS INSTRUMENTS INC

AI summary

An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.