On-Chip Power-Down Detection for Early Voltage Domain Isolation
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Solution Overview
Problem
Current systems on a chip (SoCs) face challenges in efficiently isolating voltage domains during power-down operations, leading to potential corrupted signal transmission and functional failures due to delayed and area-costly isolation signals generated externally.
Innovation Solution
The implementation of time-to-digital converter circuits within the SoC to compare voltages across different domains, generating an isolation enable signal early in the power-down process, thereby preventing corrupted signal transmission by activating isolation cells within the SoC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an isolation signal is generated externally through an I/O pad, then the isolation signal can be provided to the voltage domain, but this incurs area cost, power cost, and leakage cost associated with the I/O pad
Solution Approach 1:
The isolation signal generation function is extracted from the external PMU and moved inside the SoC to a dedicated power detection circuit. This eliminates the need to use I/O pads for signal transmission, thereby removing the area cost, power cost, and leakage cost associated with I/O pad usage while maintaining reliable isolation signal generation
Solution Approach 2:
The power detection circuit is designed to serve multiple functions: it detects voltage domain power status, generates isolation signals, and integrates these functions within the SoC fabric. This multi-functionality eliminates the need for separate external PMU and I/O pad infrastructure
2Reliability
If an isolation signal is generated externally through an I/O pad, then the isolation signal can be provided to the voltage domain, but this introduces delays in receiving the isolation signal
Solution Approach 1:
The power detection circuit continuously monitors voltage domain status and detects power-down conditions earlier than external PMU solutions. By being integrated within the SoC, the circuit can trigger isolation signal generation immediately upon detecting voltage changes, eliminating the transmission delay associated with external I/O pad signaling
3Use of energy by stationary object
If isolation signal generation is implemented within the SoC, then area and power costs are reduced, but the complexity of the internal power detection circuit increases
Solution Approach 1:
The power detection circuit is segmented into modular components: voltage sensing units, comparison logic, and isolation signal generation units. This segmentation allows for efficient resource utilization and reduces overall circuit complexity by dividing the function into manageable, reusable blocks that can be instantiated only where needed
Solution Approach 2:
The power detection circuit uses existing SoC infrastructure (voltage domains, logic elements) to perform detection and signal generation functions. By leveraging available resources within the SoC fabric rather than adding completely new dedicated hardware, the circuit achieves its function with minimized additional complexity and power overhead
4Use of energy by moving object
If current mechanisms generate isolation signal only when the whole voltage domain is at low power, then power consumption is reduced, but corrupted signals can still be transmitted during the transition phase
Solution Approach 1:
The power detection circuit detects voltage domain power-down conditions at the earliest stage of voltage transition, before the domain fully reaches low power state. This preliminary detection triggers isolation signal generation proactively, preventing corrupted signal transmission during the transition phase while maintaining power efficiency by activating isolation only when truly needed
Data Source
AI summary
A power detection circuit for detecting powering down of a voltage domain in an integrated circuit is disclosed. The power detection circuit is placed in or near the voltage domain in the integrated circuit to provide power detection on the integrated circuit. The power detection circuit detects powering down of the voltage domain to provide an isolation enable signal to another voltage domain that interfaces with the powering down voltage domain. The isolation enable signal may be used by an isolation cell coupled to the non-powering down voltage domain to prevent corrupted logic being received from the powering down voltage domain.