Power Transistor Driver Circuit for Fast Switching With Lower EMI
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Solution Overview
Problem
Existing driver circuits for power transistors face challenges in reducing electromagnetic interference (EMI) while maintaining fast switching times, as increased switching speed leads to higher EMI levels and power dissipation, and existing techniques for controlling voltage slopes result in high power-off delays.
Innovation Solution
A driver circuit with control circuitry that includes a sample and hold circuit, a gate discharge circuit, and a voltage differentiator to quickly reach the Miller zone, allowing for controlled voltage slope management and reduced delays by generating additional currents proportional to voltage differences, and an overdrive block to manage threshold voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If switching speed is increased to reduce power dissipation, then power dissipation is reduced, but electromagnetic interference level increases
Solution Approach 1:
The driver circuit dynamically adjusts the gate current in two distinct phases: initially providing a high current to quickly charge the gate capacitance and achieve fast switching, then transitioning to a lower current during the Miller plateau phase to control voltage slopes and reduce EMI. This dynamic current adjustment resolves the contradiction by optimizing both switching speed and EMI at different stages of the switching process.
Solution Approach 2:
The circuit preliminarily charges the gate capacitance with a high current before entering the Miller plateau region, ensuring that the transistor reaches the optimal switching point quickly. This preliminary high-current action reduces the overall switching time and power dissipation while allowing subsequent EMI control during the plateau phase.
2Speed
If voltage slopes are increased to improve switching speed, then switching speed is improved, but electromagnetic interference level increases
Solution Approach 1:
The driver circuit dynamically controls the gate current based on the real-time switching state. During the initial charging phase, high current produces steep voltage slopes for fast switching. During the Miller plateau phase, the current is naturally reduced, which softens the voltage slopes and reduces EMI. This dynamic adaptation resolves the contradiction between switching speed and EMI.
Solution Approach 2:
The switching process is divided into distinct periodic phases: a first phase with high current for fast charging, and a second phase with lower current for controlled discharge during the Miller plateau. This periodic structure allows the circuit to achieve fast switching initially while controlling EMI during the subsequent plateau phase.
3Object-generated harmful factors
If constant current is used to control voltage slope during Miller zone, then voltage slope is controlled, but power-off delay increases
Solution Approach 1:
Instead of using a constant current throughout the entire switching process, the driver circuit employs a dynamic current profile that transitions from high to low. During the Miller plateau phase, the current is naturally reduced to an optimal level that controls the voltage slope without causing excessive delay, resolving the contradiction between EMI control and switching speed.
Solution Approach 2:
The gate current parameter is changed during the switching process: initially set to a high value for fast charging, then transitions to a lower value during the Miller plateau. This parameter change allows the circuit to control voltage slopes and reduce EMI without incurring significant power-off delays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution optimizes current absorption and reduces delays in discharging gate capacitance, minimizing EMI and power consumption by quickly reaching the Miller zone and controlling voltage slopes, thereby enhancing switching efficiency and reducing power-off delays.
Implementation Method 1
a gate discharge circuit (6B) for generating an additional current e to discharge said capacitance CG of said gate terminal of said power transistor (2A) during a first step of said power-off process
Implementation Method 2
a voltage differentiator (6C) structured to detect the onset of the Miller effect when the power transistor (2A) operates in the saturation region
Implementation Method 3
the capacitance CGD, which is lower than the capacitance CGS in its static value, may assume a dynamic value about 20 times as high as the capacitance CGS
Data Source
AI summary
An apparatus and a method switch a load through a power transistor. The apparatus includes: a first current generator for generating a current to charge a capacitance of a control terminal of the power transistor during power on of the power transistor; a second current generator for generating a current to discharge the capacitance during power off of the power transistor. The apparatus is equipped with control circuitry having a storage element for storing a voltage value representative of the potential difference between the control terminal and a conduction terminal of the power transistor when the power transistor operates in the saturation region and a discharge circuit for generating an additional current to discharge the capacitance during the power-off process. The additional current is a function of the potential difference of the control terminal and the stored voltage value from the conduction terminal.