Power-Efficient Watchdog Timer for Embedded Systems

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Solution Overview

Problem

Watchdog timers in embedded systems often lead to unnecessary device resets, consuming power and causing frustration, as they do not differentiate between active and inactive states, resulting in resets during low power-consuming periods.

Innovation Solution

Implementing a power-efficient watchdog timer that predicts the power state of a device based on its operational mode, selectively disabling or enabling resets only when the system is active, using a combination of hardware and software components to manage the watchdog counter and issue resets only during high power-consuming states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the watchdog timer continuously monitors and resets the device without differentiation, then the system reliability is improved, but the power consumption increases unnecessarily during inactive states

Engineering Contradiction:
Improvesystem reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The watchdog timer dynamically adjusts its monitoring behavior based on the device's operational state. When the device is in an inactive or low-power state, the watchdog timer suspends or disables its monitoring function, allowing the device to remain in the low-power state without unnecessary wake-ups or resets. When the device transitions to an active state, the watchdog timer resumes monitoring. This dynamic adaptation resolves the contradiction by making the watchdog timer's power consumption variable rather than constant, maintaining reliability when needed while conserving energy during inactive periods.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the operational parameters of the watchdog timer based on device state. Specifically, the monitoring interval, timeout threshold, or enable/disable status of the watchdog timer is modified according to whether the device is active or inactive. This parameter change allows the system to maintain adequate monitoring coverage during active states while reducing or eliminating watchdog timer activity during inactive states, thereby resolving the contradiction between reliability and power consumption.

Inventive Principle:
Principle #35Parameter changes

2Stability of the object's composition

If the watchdog timer issues frequent resets, then system stability is improved, but user frustration increases due to unnecessary reboots

Engineering Contradiction:
Improvesystem stabilityVSAvoiduser frustration
Core Design Contradiction:
Stability of the object's compositionVSEase of operation

Solution Approach 1:

The watchdog timer's reset issuance behavior is made dynamic based on device state. During inactive or low-power states, the watchdog timer does not issue resets even if the timeout period elapses, recognizing that such resets would be unnecessary and frustrating to users. Resets are only issued when the device is in an active state where user interaction is expected. This dynamic behavior maintains system stability during operational periods while avoiding unnecessary disruptions during inactive periods, thereby resolving the contradiction between stability and user frustration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the reset issuance parameter of the watchdog timer based on operational context. The timeout threshold or reset enable flag is adjusted according to device state, preventing resets during inactive states while maintaining them during active states. This parameter change ensures that resets occur only when beneficial for system stability and when users would expect and appreciate the corrective action, resolving the contradiction between stability and user frustration.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If the watchdog timer monitors continuously without state differentiation, then fault detection capability is maintained, but memory and processing resources are wasted

Engineering Contradiction:
Improvefault detection capabilityVSAvoidmemory and processing resources
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The watchdog timer's monitoring activity is dynamically adjusted based on device state. During inactive states, the watchdog timer suspends or reduces its monitoring operations, freeing up memory and processing resources that would otherwise be consumed by continuous monitoring. When the device transitions to an active state, the watchdog timer resumes monitoring with appropriate sensitivity. This dynamic approach maintains fault detection capability when needed while conserving computational resources during inactive periods, resolving the contradiction between detection capability and resource consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the monitoring intensity or enable/disable status of the watchdog timer based on device operational state. During inactive states, monitoring parameters are adjusted to reduce or eliminate resource consumption. During active states, monitoring parameters are set to maintain adequate fault detection capability. This parameter adjustment resolves the contradiction by aligning resource allocation with actual monitoring needs, maintaining detection capability when resources are available and active, while conserving resources during inactive periods.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP3320438B1High availability and energy-efficient watchdog timer
Publication Date: 2019.12.18 MICROSOFT TECHNOLOGY LICENSING LLC
  • EP3320438B1 patent drawingFigure 1A
  • EP3320438B1 patent drawingFigure 1B
  • EP3320438B1 patent drawingFigure 1C

AI summary

Examples for an intelligent watchdog timer for a computing device are described herein. The watchdog timer operates a watchdog counter that repetitively counts a watchdog count interval from an initial value to a final value. The watchdog counter is continually reset if the device is functioning properly. If the watchdog timer is allowed to reach a final count value, a processor reset is initiated. Several components operate to detect the current mode of operation of the processor or an operating system, and predict, in part based on user context, when different power states may occur. The components also forecast when the watchdog timer is scheduled to reach the final count value. Based on the forecasts of when the watchdog timer will reach the final count value and the predictions of future power states of the processor or operating system, the watchdog counter is selectively disabled or reset.