Power Electronics Assembly with Stress-Relief Features
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Solution Overview
Problem
Traditional soldering techniques fail to provide suitable bonding of semiconductor devices to metal substrates in high-temperature power electronics applications, leading to delamination due to thermally-induced stresses from coefficient of thermal expansion mismatch.
Innovation Solution
A power electronics assembly with stress-relief features on the metal substrate, filled with transient liquid phase (TLP) bonding material, which mitigates thermal stresses by managing thermal expansion and contraction, using a silver-tin TLP bonding material and stress-relief features with specific dimensions and patterns to secure semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If TLP sintering is used to bond semiconductor devices to metal substrates at high temperatures, then bonding strength is improved, but thermal cooling stresses increase causing delamination
Solution Approach 1:
The metal substrate is segmented into multiple regions: a bonding area with stress-relief features and a non-bonding area without such features. This segmentation allows the bonding area to accommodate thermal stresses through the stress-relief features while maintaining strong bonding, whereas the non-bonding area provides structural support without the complexity of stress management. The segmentation resolves the contradiction by localizing stress management functions to specific regions.
Solution Approach 2:
Stress-relief features are applied locally only to the bonding area where semiconductor devices are attached, rather than uniformly across the entire substrate. This local quality approach provides stress management precisely where thermal expansion mismatch occurs most severely during TLP sintering, while maintaining substrate integrity elsewhere. The local application of stress-relief features enables strong bonding without universal substrate modification.
2Ease of manufacture
If traditional soldering techniques are used, then manufacturing simplicity is maintained, but bonding suitability fails at high operating temperatures
Solution Approach 1:
The invention changes the bonding parameters from traditional soldering temperatures to TLP sintering temperatures (280-350°C), which enables reliable bonding at high operating temperatures. Concurrently, stress-relief features are introduced to manage the thermal stresses generated by these elevated temperatures. This parameter change resolves the contradiction by enabling high-temperature bonding suitability while compensating for the increased manufacturing complexity through geometric substrate modifications.
3Reliability
If stress-relief features are added to the metal substrate, then thermal stress management is improved, but device complexity increases
Solution Approach 1:
The stress management function is extracted from the semiconductor device itself and transferred to the metal substrate through integrated stress-relief features. By taking out the stress management requirement from the device and embedding it in the substrate structure, the device remains simple while the substrate assumes the complexity of stress accommodation. This extraction resolves the contradiction by relocating complexity to a less critical component.
Solution Approach 2:
The stress-relief features are merged directly into the metal substrate structure during manufacturing, creating an integrated substrate with built-in stress management capabilities. This merging eliminates the need for separate stress-management components or complex device modifications, as the substrate itself provides both structural support and stress relief functions. The integration resolves the contradiction by combining multiple functions into a single unified structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces thermally-induced stresses, preventing delamination and ensuring reliable bonding of semiconductor devices to metal substrates, even at high operating temperatures, thereby enhancing the durability and performance of power electronics assemblies.
Implementation Method 1
TLP sintering of semiconductor devices to metal substrates utilize bonding temperatures (also referred to as sintering temperatures) between about 280° C. to about 350° C. The TLP paste at least partially melts, isothermally solidifies and forms a TLP bonding material between the semiconductor device and the metal substrate.
Implementation Method 2
The TLP paste at least partially melts, isothermally solidifies and forms a TLP bonding material between the semiconductor device and the metal substrate.
Implementation Method 3
The semiconductor devices and metal substrates have different coefficients of thermal expansion (CTE) and large thermally-induced stresses (e.g., cooling stresses) may be generated between a semiconductor device and metal substrate upon cooling from a TLP sintering temperature.
Implementation Method 4
a power electronics assembly with stress-relief features on the metal substrate, filled with transient liquid phase (TLP) bonding material, which mitigates thermal stresses by managing thermal expansion and contraction
Data Source
AI summary
A power electronics assembly includes a semiconductor device, a metal substrate, and a cooling structure. The metal substrate includes a plurality of stress-relief features that extend at least partially through a thickness of the metal substrate. The plurality of stress-relief features are at least partially filled with a transient liquid phase (TLP) bonding material. The semiconductor device is positioned over the plurality of stress-relief features and thermally bonded to the metal substrate via TLP bonding material. Vehicles having power electronics assemblies with stress-relief through-features are also disclosed.