Power Estimation Block for Virtual Prototyping Models
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Solution Overview
Problem
Current methods for power estimation in virtual prototypes of semiconductor designs are inaccurate due to the use of approximated clock signals and lack of necessary parameters, leading to inefficiencies in time, cost, and complexity, as they require model synthesis which is costly and time-consuming.
Innovation Solution
A method that estimates power consumption in virtual prototypes by using a Power Estimation Block with the real clock signal, voltage, load capacitance, leakage power, and additional design-specific parameters, allowing for more accurate calculations without full model synthesis, and includes additional timing modes for improved simulation accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If cycle-accurate simulation mode is used with real clock signal, then measurement precision of power consumption is improved, but productivity of simulation process deteriorates due to extremely slow simulation speed
Solution Approach 1:
The patent segments the simulation process into multiple timing modes (untimed, approximately timed, loosely timed, and cycle-accurate). This allows users to select appropriate simulation speed while power estimation block compensates for accuracy losses in faster modes, resolving the contradiction between simulation speed and measurement precision.
Solution Approach 2:
The power estimation block acts as an intermediary that receives simulation data from virtual prototypes and calculates power consumption using real clock signal parameters. This mediator enables accurate power measurement without requiring the entire simulation to run in slow cycle-accurate mode.
2Measurement precision
If model synthesis is performed for power estimation, then measurement precision of power consumption is improved, but loss of time and cost increases due to costly and time-consuming synthesis process
Solution Approach 1:
The patent performs preliminary extraction of power-relevant parameters (voltage, frequency, load capacitance, leakage power) from the netlist before simulation. This preliminary action enables accurate power estimation during simulation without requiring time-consuming model synthesis to be performed at runtime.
Solution Approach 2:
The patent extracts only the necessary power estimation parameters (voltage, frequency, capacitance, leakage) from the complete netlist model, separating these essential elements from the full detailed model. This extraction enables power estimation without requiring full model synthesis, reducing time and cost while maintaining accuracy.
3Productivity
If virtual prototype uses approximated clock signal, then productivity of simulation is improved due to faster simulation speed, but measurement precision of power consumption deteriorates
Solution Approach 1:
The power estimation block serves as an intermediary that receives timing information from the virtual prototype simulation and uses real clock signal parameters to calculate accurate power consumption. This allows the virtual prototype to use approximated timing for speed while power measurement maintains high precision through the mediator's use of real parameters.
Data Source
AI summary
The present invention may comprise an apparatus and method for calculating power consumption, including a unit for generating a clock-level analysis without synthesis of an algorithm description and calculating operating ratios of storage elements and arithmetic units. The invention may also comprise a method for estimating the power to be consumed by a SystemC model. By estimating this value, a user may gauge the amount of power a specific semiconductor design might consume, once manufactured into a chip.