Power Estimation System for Integrated Circuit Test Vectors
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Solution Overview
Problem
Current power analysis methods for test vectors in silicon circuits are slow and inefficient, requiring gate-level simulation or emulation, which can take weeks and are not supported by all emulators, leading to potential tester overload and silicon damage.
Innovation Solution
An integrated waveform and power engine approach that directly calculates test pattern data using initial state data from an automatic test pattern generator, eliminating the need for gate-level simulation and enabling fast, approximate power estimation by calculating power for each test vector individually and reordering patterns to meet power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If gate-level simulation with SDF delays is used to calculate power, then power estimation accuracy is improved, but computation time increases substantially (taking weeks even with compute grid)
Solution Approach 1:
The patent segments the power estimation process into two distinct phases: (1) a fast approximate power estimation using toggle activity and switching activity metrics without full simulation, and (2) a detailed power calculation only for specific patterns or cycles of interest using waveform data. This segmentation allows the system to obtain quick preliminary results and then focus computational resources only where needed, resolving the contradiction between comprehensive accuracy and computation time.
Solution Approach 2:
The patent performs preliminary power estimation using approximate methods (toggle activity, switching activity) before committing to full gate-level simulation. This preliminary action identifies patterns that exceed power thresholds, allowing the system to pre-filter test vectors and only perform detailed simulation on those that require it, thereby dramatically reducing total computation time while maintaining accuracy for critical cases.
2Measurement precision
If detailed delay information is provided for power calculation, then power estimation accuracy is improved, but emulator compatibility is reduced (emulators typically do not support detailed delay information)
Solution Approach 1:
The patent introduces an intermediary approach by using standard delay format (SDF) files as a bridge between simulation tools and power analysis. The system can process SDF-delays when available (improving accuracy) but can also operate without them using alternative methods like toggle activity and switching activity calculations. This intermediary flexibility allows the same system to work with both emulators (which may not support SDF) and simulators (which do support SDF), resolving the compatibility contradiction.
3Manufacturing precision
If test patterns are loaded serially via scan chains, then manufacturing defect visibility is improved, but peak glitch power increases (overloading tester or damaging silicon)
Solution Approach 1:
The patent applies preliminary power estimation using toggle activity and switching activity metrics to identify test patterns that will cause peak power glitches before actual testing. This preliminary analysis allows the test pattern set to be pre-processed and reordered to distribute power consumption more evenly, preventing tester overload and silicon damage during the actual scan testing while maintaining manufacturing defect visibility.
Solution Approach 2:
The patent dynamically reorders test patterns based on their estimated power characteristics. Instead of using a fixed test pattern sequence, the system analyzes power metrics and rearranges patterns to avoid consecutive high-power transitions. This dynamic reordering maintains the effectiveness of scan chain testing for defect detection while distributing power consumption to prevent peak glitches that could overload the tester or damage the silicon.
Data Source
AI summary
A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.