Power Factor Control Algorithm for Transient Noise Reduction
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Solution Overview
Problem
Existing power quality compensation devices do not effectively address line transient noise during differential capacitor changes, leading to inefficiencies in power factor correction and increased electricity costs due to low power factor penalties.
Innovation Solution
A computer-implementable control algorithm that measures reactive power, power factor, voltage, and line frequency to calculate differential compensation capacitance, minimizing line transient noise by incremental switching of capacitors and timing relay operations with voltage zero crossing for reduced disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple capacitors are switched simultaneously to correct power factor, then power factor correction speed is improved, but line transient noise increases
Solution Approach 1:
The patent segments the capacitor switching operation into multiple sequential steps, switching capacitors one by one rather than simultaneously. This divides the single large switching event into multiple smaller events, reducing the transient noise of each individual switch while achieving the same total capacitance change for power factor correction.
Solution Approach 2:
The patent implements periodic switching of capacitors with time delays between each switching event. By spacing out the switching operations periodically rather than simultaneously, the system reduces peak transient noise while still achieving the required power factor correction over a short period.
2Speed
If capacitor switching frequency is increased to respond quickly to power factor changes, then power factor correction responsiveness is improved, but switching disturbances increase
Solution Approach 1:
The patent monitors power factor continuously and prepares switching decisions in advance based on predicted needs. By anticipating when capacitance changes will be needed and preparing the switching sequence beforehand, the system can respond quickly to power factor changes while controlling the rate of switching to minimize disturbances.
Solution Approach 2:
The patent dynamically adjusts the capacitor switching strategy based on real-time power factor conditions and system state. The switching frequency and sequence are adapted dynamically rather than using fixed rates, allowing the system to respond quickly when needed while reducing switching activity when power factor is stable, thereby minimizing overall switching disturbances.
3Speed
If relay switching is performed without voltage zero crossing timing, then switching speed is improved, but switching disturbances and noise increase
Solution Approach 1:
The patent detects voltage zero crossing points in advance and schedules relay switching operations to occur at these predetermined moments. By preparing the switching command beforehand and executing it at the optimal voltage zero crossing instant, the system maintains fast response while minimizing switching disturbances caused by voltage transients.
Data Source
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AI summary
A computer-implementable control algorithm that measures: 1) the reactive power; 2) the power factor; 3) the voltage; and4) the line frequency. The algorithm calculates the differential compensation capacitance required that is either positive (capacitance to be added), or negative(capacitance to be removed). The new compensation capacitance is calculated from the sum or difference of the differential compensation capacitance and the current compensation capacitance. The algorithm compares the capacitor switching bit pattern for the current compensation capacitance and the capacitor switching bit pattern for the new compensation capacitance, and selects a capacitor switching bit map accordingly. The capacitor switch combination for the new compensation capacitance is switched in incrementally according to the capacitor switching bit map. To reach the selected capacitor switch combination, only one switch is switched at a time to minimize the line transient noise. This part of the algorithm continues to run until the PF is corrected, with the capacitor switches being switched on/off each delayed by a millisecond interval to minimize line transient noise.