Power Failure Data Backup Using Dedicated Controller and MRAM

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Solution Overview

Problem

Current RAID systems face challenges in efficiently saving data from cache memory to nonvolatile storage during power failures, particularly due to high power consumption when using high-performance processors and the limited capacity and reliability issues with NAND flash memories.

Innovation Solution

A control apparatus with a capacitor for power supply, a first nonvolatile memory, a second nonvolatile memory, and dedicated controllers for writing and verifying data, which includes a simplified error log collection mechanism using a FPGA and MRAM to manage cache data transfer during power failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a high-performance processor is used to save data from cache memory during power failure, then data backup capability is improved, but power consumption increases

Engineering Contradiction:
Improvedata backup capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent extracts the data saving function from the main processor and implements it in a dedicated save processing device. This dedicated device is specifically designed for power failure recovery operations, separating this critical function from the general-purpose processor to optimize both reliability and power consumption for this specific task.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs a simplified save processing device that uses basic logic circuits and memory elements rather than a full high-performance processor. This disposable-like approach uses simpler, lower-power components specifically for the temporary task of saving cache data during power failure, without requiring the continuous high performance of a main processor.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Reliability

If NAND flash memory is used for data backup during power failure, then data retention is improved, but capacity and reliability are limited

Engineering Contradiction:
Improvedata retentionVSAvoidstorage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments the backup storage into two distinct parts: a NAND flash memory for retaining essential system data and configuration information, and an MRAM for storing error logs and temporary backup data. This segmentation allows each storage type to be optimized for its specific function, overcoming the capacity limitations of NAND flash while maintaining its reliability for critical data.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent creates a composite storage system combining NAND flash memory and MRAM, each contributing their strengths. The NAND flash provides non-volatile storage for system essentials, while the MRAM provides high-speed, rewritable storage for error logs and temporary data, together creating a more capable backup system than either component alone.

Inventive Principle:
Principle #40Composite materials

3Reliability

If error log collection is implemented during power failure processing, then data reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The save processing device performs self-verification of written data and automatically collects error logs without external intervention. The device monitors its own operation during the power failure saving process, detecting and recording any write errors that occur, thereby improving data reliability through self-diagnosis without adding complex external monitoring systems.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent implements a feedback mechanism where the save processing device writes data to storage, verifies the write operation, and based on the verification result, either logs an error or confirms successful saving. This feedback loop ensures data reliability by detecting write failures and recording them in error logs, while keeping the logic relatively simple through direct feedback from write operations.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution reduces power consumption and increases data reliability by using a dedicated controller for save processing, while ensuring error log collection with simplified functionality, enabling effective data backup during power failures.

Implementation Method 1

a capacitor to store electric power supplied from the power supply unit and to supply the stored electric power to the control apparatus when the power supply from the power supply unit is stopped

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS8862808B2Control apparatus and control method
Publication Date: 2014.10.14 FUJITSU LTD
  • US8862808B2 patent drawing
  • US8862808B2 patent drawing
  • US8862808B2 patent drawing

AI summary

A control apparatus includes a capacitor to store electric power supplied from the power supply unit and to supply the stored electric power to the control apparatus when the power supply from the power supply unit is stopped, a first nonvolatile memory, a second nonvolatile memory, a first controller, and a second controller. The first controller writes the data, stored in the cache memory, into the first nonvolatile memory when the external power supply is stopped verifies whether the data stored in the first nonvolatile memory is normal, and sends information of area where the data in the first nonvolatile memory is not normal when the verification indicates that the writing is not normal. And the second controller writes the information sent from the first controller into the second nonvolatile memory.