Power Failure Detection Circuit Using Leakage Current
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Solution Overview
Problem
Existing power failure detection circuits in integrated circuits consume high quiescent current due to the need for a voltage division circuit with resistors and comparators, making them unsuitable for low power consumption applications.
Innovation Solution
A power failure detection circuit utilizing PMOS and NMOS FETs with a reset transistor, where the detection is based on leakage current characteristics, eliminating the need for constant power-consuming circuits, and only activating high power consumption circuits after a reset state is triggered.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a voltage division circuit with resistors and a comparator is used for power failure detection, then the detection function is reliable, but the quiescent current consumption is high
Solution Approach 1:
The patent extracts and removes the high power consumption components (resistors and comparator) from the power failure detection circuit, replacing them with a low power consumption circuit based on transistor leakage current characteristics. This extraction eliminates the need for continuous power consumption while maintaining detection functionality.
Solution Approach 2:
The patent changes the detection parameter from voltage comparison (requiring resistors and comparator) to leakage current characteristics of transistors. By utilizing the natural leakage current parameters of PMOS and NMOS transistors, the circuit achieves power failure detection without requiring continuous power supply to active components.
2Speed
If power detection circuits are always on to ensure continuous monitoring, then the detection responsiveness is fast, but the power consumption is high
Solution Approach 1:
The patent implements periodic action by using the natural oscillating leakage current characteristics of the transistor pair. The circuit periodically monitors power status through the inherent switching behavior of transistors during power transitions, eliminating the need for continuous active monitoring while maintaining detection capability.
Solution Approach 2:
The circuit uses the transistors' own leakage current as the detection signal source. The PMOS and NMOS transistors naturally exhibit different leakage current characteristics under power failure conditions, allowing the circuit to self-monitor without requiring external power-consuming active components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces power consumption under normal working voltage, making it suitable for integrated circuits with low power requirements and maintaining a reset state efficiently.
Implementation Method 1
the detection is based on leakage current characteristics
Data Source
AI summary
Disclosed is a power failure detection circuit, including a first PMOS FET (mp1), a second PMOS FET (mp2), a first NMOS FET (mn2), a second NMOS FET (mn3) and a reset transistor (mn1). The PN junction area of the drain electrode of the first PMOS FET (mp1) is greater than the PN junction area of the drain electrode of the first NMOS FET (mn2). The PN junction area of the drain electrode of the second NMOS FET (mn3) is greater than the PN junction area of the drain electrode of the second PMOS FET (mp2). The power failure detection circuit of the present invention is novel in design and high in practicability.