Power FET Gate-Drive Limiting for Startup Inrush Control
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Solution Overview
Problem
Existing DC-DC power converter architectures face issues with excessive current in-rush during startup and charge imbalance, leading to potentially damaging events such as current spikes and voltage spikes, which can overstress power switches and reduce their reliability.
Innovation Solution
The implementation of a closed-loop feedback or calibrated compensation circuit to control the gate voltage of power FETs, reducing the ON resistance and limiting current flow during startup and dynamic charge balancing, thereby mitigating damaging events without requiring additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DC-DC power converter architectures are used without additional guard circuitry, then the device complexity is low, but excessive current in-rush and voltage spikes occur during startup and dynamic reconfiguration, damaging power switches and reducing reliability
Solution Approach 1:
The current limiting function is merged with the existing gate driver circuitry by sharing the LDO power supply and control logic. The same LDO that drives the gate also provides current limiting through its inherent feedback mechanism, eliminating the need for separate protection circuitry while maintaining power switch reliability during startup and dynamic reconfiguration
Solution Approach 2:
The LDO power supply uses feedback control to regulate the gate drive voltage, which inherently limits the current through the power switch. The feedback loop adjusts the gate voltage to maintain safe operating conditions during startup and dynamic reconfiguration, preventing current in-rush and voltage spikes without requiring additional guard circuitry
2Object-generated harmful factors
If gate drive voltage is reduced to limit current during startup, then current in-rush is mitigated, but the switching speed and productivity of the power converter decrease
Solution Approach 1:
The gate drive voltage is dynamically controlled through the LDO feedback mechanism, allowing the system to adapt the voltage level based on operating conditions. During startup, the LDO naturally limits the voltage rise rate, preventing current in-rush while still enabling adequate switching speed. During normal operation, the full gate drive voltage is restored for optimal productivity
Solution Approach 2:
The LDO power supply is enabled before the main power switch to pre-charge the gate capacitance and establish safe operating conditions. This preliminary action ensures that when the power switch turns on, the gate voltage rises in a controlled manner, preventing current in-rush while maintaining subsequent switching performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively limits current through power FETs independently of switching frequency, device mismatches, and environmental variations, ensuring reliable operation and maintaining output voltage stability during dynamic reconfiguration and full load conditions.
Implementation Method 1
controlling the ON resistance, RON, of a power FET in the power converter to lower the RON of the power FET in a first ON state during normal power converter operation and to raise the RON of the power FET in a second ON state to restrict flow of current through the power FET
Data Source
AI summary
Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and/or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage VGATE applied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that VGATE is adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust VGATE; connecting to the gate of the power FET allows VGATE to be directly set.