Power Fill Mesh Cropping for IC Metal Density Control

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Solution Overview

Problem

High metal wiring density in integrated circuit layouts leads to excessive resistance and IR drop, affecting chip performance and planarization during the CMP process, making it challenging to efficiently reduce wiring density below a given threshold.

Innovation Solution

A method and apparatus that detect metal wiring density in predefined windows, crop power fill meshes iteratively until the density meets the preset threshold, ensuring sufficient power fill meshes are retained while maintaining acceptable wiring density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If power fill meshes are added to reduce resistance and IR drop, then power delivery performance is improved, but metal wiring density becomes excessively high

Engineering Contradiction:
Improvepower delivery performanceVSAvoidmetal wiring density
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies local quality by differentiating metal wiring density requirements across different regions of the chip. Power regions maintain high density for optimal power delivery, while non-power regions use reduced density. This spatial variation in density characteristics resolves the contradiction by allowing high density where needed for reliability while reducing overall quantity to prevent CMP planarization issues.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the chip layout into power regions and non-power regions using detection windows. By dividing the layout into discrete segments that can be independently analyzed and adjusted, the system can selectively add power fill meshes only in power regions, thereby improving power delivery performance without excessively increasing metal wiring density across the entire chip.

Inventive Principle:
Principle #1Segmentation

2Reliability

If metal wiring density is increased to reduce resistance, then IR drop is reduced, but CMP planarization is affected

Engineering Contradiction:
ImproveIR dropVSAvoidCMP planarization
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent implements local quality by allowing high metal wiring density in power regions where low IR drop is critical for reliability, while maintaining reduced density in non-power regions where excessive density would harm CMP planarization. This localized differentiation enables the system to optimize IR drop performance only where necessary without compromising overall manufacturability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent applies partial action by adding power fill meshes selectively only in power regions rather than uniformly across the entire chip. This partial deployment of power fill meshes achieves sufficient IR drop reduction in critical areas while avoiding excessive overall density increase that would negatively impact CMP planarization processes.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If power fill meshes are added throughout the layout, then resistance is reduced, but layout correction complexity increases

Engineering Contradiction:
ImproveresistanceVSAvoidlayout correction complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent reduces layout correction complexity by segmenting the layout into power and non-power regions using detection windows. This segmentation enables targeted analysis and correction, focusing computational resources only on power regions where power fill meshes are needed, rather than processing the entire layout uniformly. This significantly reduces the complexity of layout correction while still achieving resistance reduction goals.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by performing layout correction only in power regions identified through detection windows, rather than correcting the entire layout. This selective correction approach reduces resistance in critical power areas while minimizing the overall computational complexity and processing time required for layout correction.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11989499B2Method and apparatus for adjusting metal wiring density
Publication Date: 2024.05.21 CHANGXIN MEMORY TECH INC
  • US11989499B2 patent drawing
  • US11989499B2 patent drawing
  • US11989499B2 patent drawing

AI summary

Embodiments of the present application provide a method and an apparatus for adjusting metal wiring density. By detecting metal wiring density in each of metal density detection windows in a target layout, a region in which the metal wiring density is greater than a preset density threshold can be quickly positioned in the target layout, thereby improving the layout correction efficiency; then a power fill mesh in a target metal density detection window in which the metal wiring density is greater than the preset density threshold is cropped multiple times, until the metal wiring density in each of the metal density detection windows is less than or equal to the preset density threshold, such that sufficient power fill meshes are retained in the target layout while the metal wiring density of the target layout is less than or equal to the preset density threshold.