Multi-Transistor Power-Gate Structure for Dynamic IR Drop Mitigation
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Solution Overview
Problem
Modern circuit architectures face challenges in mitigating dynamic IR drop on internal power grids during sleep modes, which adversely impacts the performance of critical paths.
Innovation Solution
The implementation of multi-transistor power-gate schemes, including header-based, footer-based, and header-footer based power-gate structures, which utilize complementary field effect transistor (CFET) technology to mitigate dynamic IR drop on internal power and ground grids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a single transistor power-gate structure is used to cut-off external power or ground, then power consumption is reduced during sleep modes, but dynamic IR drop on internal power and ground grids increases due to simultaneous toggling of large logic gate structures
Solution Approach 1:
The patent divides the power-gate structure into multiple transistors (first transistor for power connection, second transistor for ground connection) that operate independently. This segmentation allows separate control of power and ground switching, preventing simultaneous toggling of large logic gates and thereby reducing dynamic IR drop on internal power and ground grids while maintaining power consumption benefits during sleep modes.
2Area of stationary object
If header-based or footer-based power-gate structures are used, then area efficiency is improved, but dynamic IR drop mitigation is insufficient compared to multi-transistor schemes
Solution Approach 1:
The patent combines header-based and footer-based power-gate structures into a unified multi-transistor scheme. The first transistor (header) and second transistor (footer) work together in coordination, allowing independent optimization of both power switching and ground switching. This merging provides superior dynamic IR drop mitigation compared to using either header-based or footer-based structures alone, while maintaining area efficiency through integrated design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These power-gate schemes effectively reduce dynamic IR drop, thereby improving the area and performance of circuit designs, such as memory circuits, and enhancing the overall efficiency of power management during sleep modes.
Implementation Method 1
The first transistor and the second transistor are formed with a complementary field effect transistor (CFET) technology
Data Source
AI summary
Various implementations described herein are directed to a device having a power-gate structure with multiple transistors including a first transistor and a second transistor. The first transistor may be coupled between a first voltage node and a second voltage node, and the second transistor may be coupled between the second voltage node and a third voltage node that is coupled to the second voltage node.