Power Gate Ramp-Up Bias Control for Reliable Fast Wake-Up
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Solution Overview
Problem
The initial ramp-up current of power gate transistors causes self-heating issues and reliability concerns due to excessive temperature rise, violating metal reliability limits and constraints across process, voltage, and temperature (PVT) ranges, limiting the minimum and maximum size of power gate transistors that can be turned on.
Innovation Solution
Dividing the array of power gate transistors into slices and using digital control to progressively turn them on with discrete ramp-up biases, maintaining a constant or near-constant current to avoid violating performance parameters, and switching to a ground bias once the target voltage is reached, allowing for faster ramp-up times while ensuring reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the power gate transistor is turned on quickly to reduce latency, then the ramp-up time is reduced, but the initial ramp-up current causes self-heating issues and violates metal reliability limits
Solution Approach 1:
The power gate transistor array is divided into multiple slices (first slice, second slice, third slice) that are activated sequentially rather than simultaneously. This segmentation allows the total ramp-up current to be distributed over time, reducing the peak current stress on any single slice while maintaining overall fast activation. The controller activates slices in a controlled sequence, achieving both fast response and reliability.
2Power
If the power gate transistor size is increased to provide higher current, then the power delivery capability is improved, but the initial ramp-up current exceeds safe levels causing self-heating
Solution Approach 1:
The power gate transistor array is divided into multiple slices that are activated sequentially. This allows the total power delivery capability to be maintained through the combined capacity of all slices, while the sequential activation ensures that the current through any individual slice remains within safe temperature limits. The controller manages the activation sequence to balance power delivery with thermal constraints.
3Temperature
If the ramp-up current is limited to prevent self-heating, then the temperature control is improved, but the ramp-up time increases due to slower current increase
Solution Approach 1:
The power gate transistor array is divided into multiple slices activated sequentially at controlled time intervals. This segmentation enables the ramp-up current to be maintained within safe temperature limits for each slice while achieving fast overall activation through parallel slice activation. The controller optimizes the activation timing to balance temperature control with minimal ramp-up time.
Solution Approach 2:
The controller pre-plans and executes a sequential activation sequence for the power gate slices. By preparing and executing this predetermined sequence, the system achieves optimal ramp-up performance that balances temperature constraints with speed requirements, avoiding both excessive heating and unnecessarily slow activation.
4Power
If the power gate transistor size is increased to provide higher current, then the power delivery is improved, but the maximum current causes excessive droop on the ungated power supply node
Solution Approach 1:
The power gate transistor array is divided into multiple slices that are activated sequentially rather than simultaneously. This segmentation distributes the total current draw over time, preventing excessive instantaneous current that would cause droop on the ungated power supply node. The controller manages the activation sequence to maintain power supply stability while achieving the required power delivery capability.
Data Source
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AI summary
An apparatus is provided which comprises: a power gate device coupled to a gated power supply node and an ungated power supply node; and a control circuitry coupled to the power gate device, wherein the control circuitry is to turn on the power gate device by providing at least two bias voltages separated in time to gradually turn on the power gate device.