Power Gate Sequencing for Stable Multi-Core IC Activation
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Solution Overview
Problem
Activating or shutting down a core in integrated circuits can dramatically affect the performance of other cores due to voltage and current interference, as the main power source struggles to instantaneously supply the required current, leading to power being drawn from active cores during transient periods.
Innovation Solution
Implementing power gates along the power path with a nonlinear rate of impedance change to control current delivery, reducing the impact on other cores by gradually activating or deactivating power gates to manage impedance and limit current draw during core activation or deactivation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a core is activated instantaneously, then the activation time is reduced, but the peak current draw from other active cores increases dramatically
Solution Approach 1:
The power gate is activated in a staged manner rather than instantaneously. The activation process is divided into multiple phases: initial activation phase where the power gate starts conducting, intermediate phase where it gradually increases conductivity, and final phase where it reaches full conductivity. This periodic/staged action reduces the peak current draw while maintaining reasonable activation time.
Solution Approach 2:
The power gate's impedance is dynamically adjusted during the activation process. Instead of being static, the impedance changes over time to match the power source's ability to supply current. The power gate transitions from high impedance to low impedance gradually, allowing the system to adapt to the transient power demands without causing harmful current draws from other cores.
2Speed
If the main power source supplies current instantaneously, then the response time is improved, but the voltage stability of active cores deteriorates
Solution Approach 1:
The power gate acts as an intermediary between the main power source and the cores. It mediates the current flow by controlling its impedance, preventing direct instantaneous current draws from affecting other cores. The power gate absorbs and smooths the transient effects, protecting the voltage stability of active cores while still enabling fast power delivery when needed.
Solution Approach 2:
The power gate provides beforehand cushioning by being in a controlled impedance state before full activation. During the transition period, it gradually adjusts its impedance to cushion the shock of current demand changes. This prevents sudden voltage drops that would otherwise affect active cores, cushioning the system against transient disturbances before they can propagate.
3Productivity
If power gates are activated rapidly, then the productivity is improved, but the current interference with other cores increases
Solution Approach 1:
The power gate's electrical parameters (impedance, conductivity) are changed in a controlled sequence during activation. Instead of abrupt parameter changes that cause interference, the parameters are modified progressively through defined stages. This allows rapid overall activation while maintaining acceptable current interference levels throughout the transition process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the peak current drawn from other cores during activation, minimizing performance drops and maintaining stable operation, with simulations showing over 50% reduction in current draw and preventing frequency drops by up to 170 MHz.
Implementation Method 1
controlling a combined impedance of a plurality of power gates allocated to the first power consuming portion
Data Source
AI summary
An integrated circuit may include multiple power consuming cores, multiple sets of power gates, and a control circuit. Each set of power gates can be configured to provide one or more power paths to provide power to a corresponding power consuming core. The control circuit can be configured to switch the set of power gates allocated to a power consuming core in a sequence of switching events during an activation period in response to one of the power consuming cores being turned on or off. The sequence of switching events may vary the number of power gates being switched or vary a time interval between the switching events.