Power Gate Switching System for Voltage Drop Mitigation

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Solution Overview

Problem

Semiconductor devices face challenges in maintaining stable operation due to voltage drops in standard cells far from the power gate switch, leading to potential malfunction as they do not receive the same level of power voltage as cells closer to the switch.

Innovation Solution

A power gate switching system is designed with a virtual power line and n-well configuration, including specific power gate switch cells with and without taps, arranged in rows to ensure uniform power distribution and prevent latch-up phenomena, using diffusion regions and gate electrodes to stabilize voltage supply.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If power voltage is supplied from a single power gate switch, then device complexity is reduced, but voltage drop occurs in standard cells far from the power gate switch

Engineering Contradiction:
Improvepower gate switch configurationVSAvoidvoltage stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The power gate switching system is divided into multiple segments along the virtual power line. Each segment contains power gate switch cells that independently regulate voltage, breaking the long power distribution path into shorter segments to minimize voltage drops in distant standard cells.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Additional power gate switch cells are introduced as intermediary components between the main power gate switch and distant standard cells. These intermediary cells act as voltage regulation stations, ensuring stable voltage supply to remote areas of the semiconductor device.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If additional power gate switch cells are added to reduce voltage drop, then voltage stability is improved, but device complexity increases

Engineering Contradiction:
Improvevoltage stabilityVSAvoidpower gate switch configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple power gate switch cells are merged into a coordinated system along the virtual power line. The cells work together as an integrated power distribution network, where each cell contributes to overall voltage stability without requiring independent control, thus managing complexity through systematic integration.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Power gate switch cells are strategically placed at specific locations along the virtual power line where voltage drops are most likely to occur. This localized approach ensures voltage stability is provided precisely where needed, rather than uniformly throughout the entire device, optimizing the balance between reliability and complexity.

Inventive Principle:
Principle #3Local quality

3Reliability

If power gate switch cells are placed throughout the device, then voltage distribution is improved, but area efficiency decreases

Engineering Contradiction:
Improvepower voltage uniformityVSAvoidchip size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Instead of placing power gate switch cells throughout the entire device, the system uses partial action by positioning cells only at critical locations along the virtual power line where voltage regulation is most needed. This selective placement maintains voltage uniformity while minimizing the area occupied by power gate infrastructure.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10680015B2Power gate switching system
Publication Date: 2020.06.09 SAMSUNG ELECTRONICS CO LTD
  • US10680015B2 patent drawing
  • US10680015B2 patent drawing
  • US10680015B2 patent drawing

AI summary

A semiconductor device includes: a virtual power line extended in a first direction; an n-well extended in the first direction, wherein the virtual power line and the n-well are disposed in a row; a first power gate switch cell disposed in the n-well; a second power gate switch cell disposed in the n-well, wherein the first and second power gate switch cells are first type cells; and a third power gate switch cell disposed in the n-well between the first and second power gate switch cells, wherein the third power gate switch cell is a second type cell different from the first type cells.